Browse > Article

저전력 디지털 신호처리 가속기 설계 기술  

Jeon, Dong-Seok (서울대학교)
Publication Information
The Magazine of the IEIE / v.44, no.6, 2017 , pp. 32-41 More about this Journal
Keywords
Citations & Related Records
연도 인용수 순위
  • Reference
1 http://ifixit.org/blog/8409/iphone-7-and-7-plus-internalswallpapers/
2 G. Chen et al., "Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2010, pp. 288-289.
3 B. Zhai et al., "Theoretical and Practical Limits of Dynamic Voltage Scaling," in Proc. Design Automation Conf., May 2005, pp. 868-873.
4 D. Jeon et al., "A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 23-34, Jan. 2012.   DOI
5 D. G. Lowe, "Object recognition from local scale-invariant features," in Proc. IEEE Int. Conf. on Computer Vision, Sep. 1999, pp. 1150-1157.
6 H. Bay et al., "SURF: Speeded Up Robust Features," Computer Vision and Image Understanding, vol. 110, no. 3, pp. 346-359, 2008.   DOI
7 S. Shen et al., "Autonomous Multi-Floor Indoor Navigation with a Computationally Constrained MAV," in Proc. IEEE Conf. on Robotics and Automation, May 2011, pp. 20-25.
8 G. Grisetti et al., "Improving Grid-based SLAM with Rao-Blackwellized Particle Filters by Adaptive Proposals and Selective Resampling," in Proc. IEEE Conf. on Robotics and Automation, Apr. 2005, pp. 2432-2437.
9 D. Jeon et al., "An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS," IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1271-1284, May. 2014.   DOI
10 D. Jeon et al., "A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS," IEEE J. Solid- State Circuits, to appear.
11 A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005.   DOI
12 M. Schwarz, H. Schulz, and S. Behnke, "RGB-D object recognition and pose estimation based on pre-trained convolutional neural network features," in Proc. IEEE International Conference on Robotics and Automation, May. 2015, pp. 1329-1335.
13 A. Krizhevsky, I. Sutskever, and G. E. Hinton, "Imagenet classification with deep convolutional neural networks," in Proc. Advances in Neural Information Processing Systems, Dec. 2012, pp. 1-9.
14 N. Sumi, A. Baba, and V. G. Moshnyaga, "Effect of computation offload on performance and energy consumption of mobile face recognition," in Proc. IEEE Workshop on Signal Processing Systems, Oct. 2014, pp. 1-7.
15 P. Viola and M. Jones, "Rapid Object Detection using a Boosted Cascade of Simple Features," in Proc. IEEE Conf. on Computer Vision and Pattern Recognition, Dec. 2001, pp. 511-518.
16 M. A. Turk and A. P. Pentland, "Face recognition using eigenfaces," in Proc. IEEE Conf. on Computer Vision and Pattern Recognition, Jun. 1991, pp. 511-518.
17 Y.-H. Chen et al., "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2016, pp. 262-263.
18 D. Shin et al., "DNPU: An 8.1TOPS/W Reconfigurable CNN-RNN Processor for General-Purpose Deep Neural Networks," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2017, pp. 240-241.
19 J. Chung and T. Shin, "Simplifying Deep Neural Networks for Neuromorphic Architectures", in Proc. IEEE/ACM Design Automation Conference (DAC), June 2016, pp. 1-6.
20 J. Sim et al., "A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2016, pp. 264-265.
21 P. A. Whatmough et al., "A 28nm SoC with a 1.2GHz 568nJ/Prediction Sparse Deep-Neural-Network Engine with >0.1 Timing Error Rate Tolerance for IoT Applications," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2017, pp. 242-243.
22 S. Bang et al., "A $288{\mu}W$ Programmable Deep-Learning Processor with 270KB On-Chip Weight Storage Using Non-Uniform Memory Hierarchy for Mobile Intelligence," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2017, pp. 250-251.