1 |
Y. Takai, M. Fukuchi, R. Kinoshita, C. Matsui, K. Takeuchi, "Analysis on Heterogeneous SSD Configuration with Quadruple-Level 셀 (QLC) NAND Flash Memory," 2019 IEEE 11th International Memory Workshop (IMW), June 2019. DOI: 10.1109/IMW.2019.8739689
|
2 |
S.W Choi, K.T Park, M. Passerini, H.J Park, D.Y Kim, C.H Kim, K.W Park, J.W, Kim "A 셀 current compensation scheme for 3D NAND FLASH memory," 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), January 2016. DOI: 10.1109/ASSCC.2015.7387432
|
3 |
Hang-Ting Lue, "3D NAND flash memory," https://patents.google.com/patent/US9018047B2/en
|
4 |
A. Soga, C. Sun, K. Takeuchi, "NAND flash aware data management system for high-speed SSDs by garbage collection overhead suppression," 2014 IEEE 6th International Memory Workshop (IMW), May 2014. DOI: 10.1109/IMW.2014.6849374
|
5 |
T.S Chung, D.J Park, S.W Park, D.H Lee, S.W Lee, and H.J Song, "A survey of Flash Translation Layer," Journal of Systems Architecture, Vol. 55, No. 5, pp. 332-343, April 2009. DOI: https://doi.org/10.1016/j.sysarc.2009.03.005
DOI
|
6 |
S.J Kwon, A. Ranjitkar, Y.B Ko, and T.S Chung, "FTL algorithms for NAND-type flash memories," Design Automation for Embedded Systems, Vol. 15, No. 3-4, pp. 191-224, March 2011. DOI: https://doi.org/10.1007/s10617-011-9071-9
DOI
|
7 |
D. Ma, J. Feng, and G. Li, "A Survey of Address Translation Technologies for Flash Memories," ACM Computing Surveys (CSUR), Vol. 46, No. 3, pp. 1-39, January 2014. DOI: https://doi.org/10.1145/2512961
|
8 |
S.W Lee, D.J Park, T.S Chung, D.H Lee, S.W Park, H.J Song, "A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation," ACM Transactions on Embedded Computing Systems, Vol. 6, No. 3, July 2007. DOI: https://doi.org/10.1145/1275986.1275990
|
9 |
Y. Wang, Z. Qin, R. Chen, Z. Shao, Q. Wang, S. Li, L.T. Yang, "A Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems," IEEE Transactions on Multi-Scale Computing Systems Vol. 2, No. 1, pp. 17-29, March 2016. DOI: 10.1109/TMSCS.2016.2516015
DOI
|
10 |
Y. Hu, H. Jiang, D. Feng, L. Tian, S. Zhang, J. Liu, W. Tong, Y. Qin, L. Wang, "Achieving page-mapping FTL performance at block-mapping FTL cost by hiding address translation," 2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST), pp. 1-12, June 2010. DOI: 10.1109/MSST.2010.5496970
|
11 |
D.W Jung, J.U Kang, H.S Jo, J.S Kim, and J.W Lee, "Superblock FTL: A Superblock-Based Flash Translation Layer with a Hybrid Address Translation Scheme," ACM Transactions on Embedded Computing Systems (TECS), Vol. 9, No. 4, April 2010. DOI: https://doi.org/10.1145/1721695.1721706
|
12 |
S.W Lee, K.W Ryu, "Block Unit Mapping Technique of NAND Flash Memory Using Variable Offset," Journal of The Korea Society of Computer and Information Vol. 24 No. 8, pp. 9-17 August 2019. DOI : http://dx.doi.org/10.9708/jksci.2019.24.08.009
DOI
|
13 |
Y.J Kim, B. Tauras, A. Gupta, B. Urgaonkar, "FlashSim: A Simulator for NAND Flash-Based Solid-State Drives," 2009 First International Conference on Advances in System Simulation, October 2009. DOI: 10.1109/SIMUL.2009.17
|