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http://dx.doi.org/10.9708/jksci.2014.19.10.001

Design Space Exploration of Many-Core Processor for High-Speed Cluster Estimation  

Seo, Jun-Sang (School of Electrical Engineering, University of Ulsan)
Kim, Cheol-Hong (School of Electronics and Computer Engineering, Chonnam National University)
Kim, Jong-Myon (School of Electrical Engineering, University of Ulsan)
Abstract
This paper implements and improves the performance of high computational subtractive clustering algorithm using a single instruction, multiple data (SIMD) based many-core processor. In addition, this paper implements five different processing element (PE) architectures (PEs=16, 64, 256, 1,024, 4,096) to select an optimal PE architecture for the subtractive clustering algorithm by estimating execution time and energy efficiency. Experimental results using two different medical images and three different resolutions ($128{\times}128$, $256{\times}256$, $512{\times}512$) show that PEs=4,096 achieves the highest performance and energy efficiency for all the cases.
Keywords
Cluster estimation; Subtractive clustering algorithm; Parallel processing; Many-core architecture;
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Times Cited By KSCI : 6  (Citation Analysis)
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