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http://dx.doi.org/10.9708/jksci/2012.17.10.011

The Compressed Instruction Set Architecture for the OpenRISC Processor  

Kim, Dae-Hwan (Dept. of Computer Information, Suwon Science College)
Publication Information
Journal of the Korea Society of Computer and Information / v.17, no.10, 2012 , pp. 11-23 More about this Journal
Abstract
To achieve efficient code size reduction, this paper proposes a new compressed instruction set architecture for the OpenRISC architecture. The new instructions and their corresponding formats are designed by the profiling information of the existing instruction usage. New 16-bit instructions and 32-bit instructions are proposed to compressed the existing 32-bit instructions and instruction sequences, respectively. The proposed instructions can be classified into three types. The first is the new 16-bit instructions for the frequent normal 32-bit instructions such as add, load, store, branch, and jump instructions. The second type is the new 32-bit instructions for the consecutive two load instructions, two store instructions, and 32-bit data mov instructions. Finally, two new 32-bit instructions are proposed to compress function prolog and epilog code, respectively. OpenRISC hardware decoder is extended to support the new instructions. Experiments show that the efficiency of code size reduction improves by an average of 30.4% when compared to the OR1200 instruction set architecture without loss of execution performance.
Keywords
Instruction set design; Code size; Embedded processor; OpenRISC; OR1200;
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Times Cited By KSCI : 4  (Citation Analysis)
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