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| 1 |
Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory
Kim, Seunghyun;Kwon, Dae Woong;Lee, Sang-Ho;Park, Sang-Ku;Kim, Youngmin;Kim, Hyungmin;Kim, Young Goan;Cho, Seongjae;Park, Byung-Gook;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.167-173,
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| 2 |
CMOS Analog Integrate-and-fire Neuron Circuit for Driving Memristor based on RRAM
Kwon, Min-Woo;Baek, Myung-Hyun;Park, Jungjin;Kim, Hyungjin;Hwang, Sungmin;Park, Byung-Gook;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.174-179,
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| 3 |
A Study on Shear-stress Calibration by the Mid-point Measurements in +45/-45 Degree Semiconductor Resistor-pair
Cho, Chun-Hyung;Cha, Ho-Young;Sung, Hyuk-Kee;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.180-185,
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| 4 |
Implementation of an Integrated Pressure-sensor System Adapted to the Optimum Sensitivity
Hong, Sung-Hee;Cho, Chun-Hyung;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.186-191,
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| 5 |
Optimization of Double Gate Vertical Channel Tunneling Field Effect Transistor (DVTFET) with Dielectric Sidewall
WANG, XIANGYU;Cho, Wonhee;Baac, Hyoung Won;Seo, Dongsun;Cho, Il Hwan;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.192-198,
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| 6 |
Mutually-Actuated-Nano-Electromechanical (MA-NEM) Memory Switches for Scalability Improvement
Lee, Ho Moon;Choi, Woo Young;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.199-203,
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| 7 |
AlGaN/GaN-on-Si Power FET with Mo/Au Gate
Kim, Hyun-Seop;Jang, Won-Ho;Han, Sang-Woo;Kim, Hyungtak;Cho, Chun-Hyung;Oh, Jungwoo;Cha, Ho-Young;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.204-209,
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| 8 |
Implementation of Neuromorphic System with Si-based Floating-body Synaptic Transistors
Park, Jungjin;Kim, Hyungjin;Kwon, Min-Woo;Hwang, Sungmin;Baek, Myung-Hyun;Lee, Jeong-Jun;Jang, Taejin;Park, Byung-Gook;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.210-215,
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| 9 |
Si1-xGex Positive Feedback Field-effect Transistor with Steep Subthreshold Swing for Low-voltage Operation
Hwang, Sungmin;Kim, Hyungjin;Kwon, Dae Woong;Lee, Jong-Ho;Park, Byung-Gook;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.216-222,
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| 10 |
Design and Analysis of AlGaN/GaN MIS HEMTs with a Dual-metal-gate Structure
Jang, Young In;Lee, Sang Hyuk;Seo, Jae Hwa;Yoon, Young Jun;Kwon, Ra Hee;Cho, Min Su;Kim, Bo Gyeong;Yoo, Gwan Min;Lee, Jung-Hee;Kang, In Man;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.223-229,
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| 11 |
InGaAs-based Tunneling Field-effect Transistor with Stacked Dual-metal Gate with PNPN Structure for High Performance
Kwon, Ra Hee;Lee, Sang Hyuk;Yoon, Young Jun;Seo, Jae Hwa;Jang, Young In;Cho, Min Su;Kim, Bo Gyeong;Lee, Jung-Hee;Kang, In Man;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.230-238,
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| 12 |
Experimental Investigation of Physical Mechanism for Asymmetrical Degradation in Amorphous InGaZnO Thin-film Transistors under Simultaneous Gate and Drain Bias Stresses
Jeong, Chan-Yong;Kim, Hee-Joong;Lee, Jeong-Hwan;Kwon, Hyuck-In;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.239-244,
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| 13 |
Investigation of Nb-Zr-O Thin Film using Sol-gel Coating
Kim, Joonam;Haga, Ken-ichi;Tokumitsu, Eisuke;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.245-251,
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| 14 |
Methodology for Extracting Trap Depth using Statistical RTS Noise Data of Capture and Emission Time Constant
Oh, Dong-Jun;Kwon, Sung-Kyu;Song, Hyeong-Sub;Kim, So-Yeong;Lee, Ga-Won;Lee, Hi-Deok;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.252-259,
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| 15 |
Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory
Baek, Myung-Hyun;Kim, Do-Bin;Kim, Seunghyun;Lee, Sang-Ho;Park, Byung-Gook;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.260-264,
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| 16 |
Electrical Characteristics of SiO2/4H-SiC Metal-oxide-semiconductor Capacitors with Low-temperature Atomic Layer Deposited SiO2
Jo, Yoo Jin;Moon, Jeong Hyun;Seok, Ogyun;Bahng, Wook;Park, Tae Joo;Ha, Min-Woo;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.265-270,
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| 17 |
Triple-gate Tunnel FETs Encapsulated with an Epitaxial Layer for High Current Drivability
Lee, Jang Woo;Choi, Woo Young;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.271-276,
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| 18 |
A Study on Thermal Stability Improvement in Ni Germanide/p-Ge using Co interlayer for Ge MOSFETs
Shin, Geon-Ho;Kim, Jeyoung;Li, Meng;Lee, Jeongchan;Lee, Ga-Won;Oh, Jungwoo;Lee, Hi-Deok;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.277-282,
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| 19 |
Contact Resistance Reduction between Ni-InGaAs and n-InGaAs via Rapid Thermal Annealing in Hydrogen Atmosphere
Lee, Jeongchan;Li, Meng;Kim, Jeyoung;Shin, Geonho;Lee, Ga-won;Oh, Jungwoo;Lee, Hi-Deok;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.283-287,
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| 20 |
Transient Simulation of Graphene Sheets using a Deterministic Boltzmann Equation Solver
Hong, Sung-Min;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.288-293,
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| 21 |
A Reconfigurable 4th Order ΣΔ Modulator with a KT/C Noise Reduction Circuit
Yang, Su-Hun;Seong, Jae-Hyeon;Yoon, Kwang-Sub;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.294-301,
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| 22 |
Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder
Guduri, Manisha;Islam, Aminul;
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The Institute of Electronics and Information Engineers
, v.17, no.2, pp.302-317,
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