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Journal of the Institute of Electronics Engineers of Korea SD  

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1 Depletion region analysis of silicon substrate using finite element methods
Byeon, Gi-Ryang;Hwang, Ho-Jeong; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.1-11,
2 Analytical Breakdown Voltage for 4H-SiC ${p^+}$ Junction
Jeong, Yong-Seong; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.12-17,
3 Studies on the Fabrication of 0.2 ${\mu}m$Wide-Head T-Gate PHEMT′s
Jeon, Byeong-Cheol;Yun, Yong-Sun;Park, Hyeon-Chang;Park, Hyeong-Mu;Lee, Jin-Gu; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.18-24,
4 Studies on the deposition of ${Si_3}{N_4}$ for the passivation of PHEMT's
Sin, Jae-Wan;Park, Hyeon-Chang;Park, Hyeong-Mu;Lee, Jin-Gu; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.25-30,
5 Effects of $C_2F_{6}$ Gas on Via Etching Characteristics
Ryu, Ji-Hyeong;Park, Jae-Don;Yun, Gi-Wan; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.31-38,
6 High-sensitivity temperature sensor using the side polished single mode fiber and polymer planar waveguide coupler
Jeong, Ung-Gyu;Kim, Sang-U;Kim, Gwang-Taek;Kim, Eung-Su;Yu, Yun-Sik;Gang, Sin-Won; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.39-46,
7 XPM mode Wavelength Converter using Polarization Controller and SOA within Optical Fiber Loop Mirror
Lee, Seung-U;Lee, Jeong-Yeol;Yun, Gyeong-Mo;Lee, Yong-Gi;Eom, Jin-Seop; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.47-57,
8 A Study on the Acousto-Optical Wavelength Tunable Filters Utilizing Tapered Directional Coupler SAW Guides
Jeong, Gi-Jo;Kim, Jeong-Hui;Jeong, Hong-Sik; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.58-66,
9 Modeling Interconnect Wiring using the Partial Element Equivalent Circuit Approach in Time Domain
Park, Seol-Cheon;Yun, Seok-In;Won, Tae-Yeong; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.67-75,
10 Design of a Full-Adder Using Current-Mode Multiple-Valued Logic CMOS Circuits
Lee, Yong-Seop;Gwak, Cheol-Ho;Kim, Jeong-Beom; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.76-82,
11 Linearity Enhancement of Partially Doped Channel GaAs-based Double Heterostructure Power FETs
Kim, U-Seok;Kim, Sang-Seop;Jeong, Yun-Ha; / The Institute of Electronics and Information Engineers , v.39, no.1, pp.83-88,