ETRI Journal

  • 제46권3호
  • /
  • Pages.550-563
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  • 2024
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  • 1225-6463(pISSN)
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  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
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Electronically tunable compact inductance simulator with experimental verification

  • Kapil Bhardwaj (Department of Electronics and Communication Engineering, National Institute of Technology Jamshedpur) ;
  • Mayank Srivastava (Department of Electronics and Communication Engineering, National Institute of Technology Jamshedpur) ;
  • Anand Kumar (Department of Electronics and Communication Engineering, National Institute of Technology Jamshedpur) ;
  • Ramendra Singh (Department of CSE (IOT), Raj Kumar Goel Institute of Technology) ;
  • Worapong Tangsrirat (Department of Instrumentation and Control Engineering, King Mongkut's Institute of Technology Ladkrabang)
  • 투고 : 2023.01.15
  • 심사 : 2023.03.15
  • 발행 : 2024.06.20
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초록

A novel inductance simulation circuit employing only two dual-output voltage-differencing buffered amplifiers (DO-VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor-less realization that provides electronically controllable realized inductance through biasing quantities of DO-VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO-VDBAs and does not exhibit instability at high frequencies. The simple and compact metal-oxide semiconductor (MOS) implementation of the DO-VDBAs (eight MOS per DO-VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on-chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF-356.

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참고문헌

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