Nuclear Engineering and Technology

  • 제56권11호
  • /
  • Pages.4679-4687
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  • 2024
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  • 1738-5733(pISSN)
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  • 2234-358X(eISSN)
한국원자력학회 (Korean Nuclear Society)
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Radiation effects on multi-channel Forksheet-FET and Nanosheet-FET considering the bottom dielectric isolation scheme

  • Gunhee Choi (Department of Electrical and Computer Engineering, Sungkyunkwan University) ;
  • Jongwook Jeon (Department of Electrical and Computer Engineering, Sungkyunkwan University)
  • 투고 : 2024.03.07
  • 심사 : 2024.06.18
  • 발행 : 2024.11.25
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초록

This study analyzes the single-event transient (SET) characteristics of alpha particles on multi-channel Forksheet-FET and Nanosheet-FET at the device and circuit levels through 3D TCAD simulations. The study investigates the differences in SET responses based on the energy and incident position of incoming alpha particles, considering the structural variances between Forksheet-FET and Nanosheet-FET, as well as the presence or absence of bottom dielectric isolation (BDI) in the fabrication process. Specifically, the introduction of BDI is observed to significantly suppress the voltage drop caused by 'unintended' current, as it can block the substantial electron-hole pairs (EHP) generated by injected alpha particles in the bulk substrate from reaching the FET terminals. Furthermore, it was confirmed that the size of abnormal current decreases as the energy of the injected alpha particle increases. Additionally, evaluating the response to SET based on the fundamental logic circuit, the CMOS inverter, revealed relatively small abnormal voltage drops for both Forksheet and Nanosheet when BDI was applied, confirming high immunity to radiation effects. Moreover, it can be observed that the application of BDI enhances reliability from a memory perspective by effectively suppressing voltage flips in the SRAM's cross-coupled latch circuit.

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과제정보

Authors are thankful to IC Design Education Center (IDEC) for EDA tool supports. This paper was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2022M3F3A2A01072215).

참고문헌

  1. G.E. Moore, Cramming more components onto integrated circuits, Proc. IEEE 86 (1) (1998) 82-85.
  2. W.-K. Chen, Linear Networks and Systems. Belmont, CA, USA: Wadsworth, 1993, pp. 123-135.
  3. R.H. Dennard, F.H. Gaensslen, H.-N. Yu, V.L. Rideout, E. Bassous, A.R. LeBlanc, Design of ion-implanted MOSFET's with very small physical dimensions, IEEE J. Solid State Circ. 9 (5) (October 1974) 256-268, https://doi.org/10.1109/JSSC.1974.1050511.
  4. N. Loubet, et al., Stacked Nanosheet gate-all-around transistor to enable scaling beyond FinFET, in: 2017 Symposium on VLSI Technology, IEEE, 2017.
  5. Daniel Nagy, et al., Benchmarking of FinFET, Nanosheet, and nanowire FET architectures for future technology nodes, IEEE Access 8 (2020) 53196-53202. https://doi.org/10.1109/ACCESS.2020.2980925
  6. Lei Cao, et al., Bottom dielectric isolation to suppress sub-fin parasitic channel of vertically-stacked horizontal gate-all-around Si nanosheets devices, in: 2022 China Semiconductor Technology International Conference (CSTIC), IEEE, 2022.
  7. J. Zhang, et al., Full bottom dielectric isolation to enable stacked Nanosheet transistor for low power and high performance applications, in: 2019 IEEE International Electron Devices Meeting (IEDM), IEEE, 2019.
  8. Pieter Weckx, et al., Novel Forksheet device architecture as ultimate logic scaling device towards 2nm, in: 2019 IEEE International Electron Devices Meeting (IEDM), IEEE, 2019.
  9. H. Mertens, et al., Forksheet FETs with bottom dielectric isolation, self-aligned gate cut, and isolation between adjacent source-drain structures, in: 2022 International Electron Devices Meeting (IEDM), IEEE, 2022.
  10. Robert C. Baumann, Radiation-induced soft errors in advanced semiconductor technologies, IEEE Trans. Device Mater. Reliab. 5 (3) (2005) 305-316. https://doi.org/10.1109/TDMR.2005.853449
  11. Jianjun Chen, et al., Novel layout technique for N-hit single-event transient mitigation via source-extension, IEEE Trans. Nucl. Sci. 59 (6) (2012) 2859-2866. https://doi.org/10.1109/TNS.2012.2212457
  12. Kodai Yamada, et al., Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process, in: 2018 IEEE International Reliability Physics Symposium (IRPS), IEEE, 2018.
  13. Gaurav Kaushal, et al., Radiation effects in Si-NW GAA FET and CMOS inverter: a TCAD simulation study, IEEE Trans. Electron. Dev. 59 (5) (2012) 1563-1566. https://doi.org/10.1109/TED.2012.2187656
  14. Jungsik Kim, et al., Single-event transient in FinFETs and nanosheet FETs, IEEE Electron. Device Lett. 39 (12) (2018) 1840-1843. https://doi.org/10.1109/LED.2018.2877882
  15. Nischal Anand, et al., TCAD-based analysis of nanosheet and forksheet FET electrical characteristics in the presence of gamma and heavy ion radiation, in: 2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC) 1, IEEE, 2023.
  16. Xun-Ting Zheng, Vita Pi-Ho Hu, Improved radiation hardness for nanosheet FETs with partial bottom dielectric isolation, in: 2023 Silicon Nanoelectronics Workshop (SNW), IEEE, 2023.
  17. Patrick Nsengiyumva, et al., Analysis of bulk FinFET structural effects on single-event cross sections, IEEE Trans. Nucl. Sci. 64 (1) (2016) 441-448.
  18. Patrick Nsengiyumva, et al., A comparison of the SEU response of planar and FinFET D flip-flops at advanced technology nodes, IEEE Trans. Nucl. Sci. 63 (1) (2016) 266-272. https://doi.org/10.1109/TNS.2015.2508981
  19. Yung-Chun Wu, et al., "Introduction of Synopsys Sentaurus TCAD simulation." 3D TCAD Simulation for CMOS Nanoeletronic Devices, 2018, pp. 1-17.
  20. Michiel Vandemaele, et al., Simulation comparison of hot-carrier degradation in nanowire, Nanosheet and Forksheet FETs, in: 2022 IEEE International Reliability Physics Symposium (IRPS), IEEE, 2022.
  21. Changhyun Yoo, et al., Analysis of self-heating effects in multi-Nanosheet FET considering bottom isolation and package options, IEEE Trans. Electron. Dev. 69 (3) (2022) 1524-1531. https://doi.org/10.1109/TED.2022.3141327
  22. Daisuke Kobayashi, Scaling trends of digital single-event effects: a survey of SEU and SET parameters and comparison with transistor performance, IEEE Trans. Nucl. Sci. 68 (2) (2020) 124-148. https://doi.org/10.1109/TNS.2020.3044659
  23. Youngsoo Seo, et al., Prediction of alpha particle effect on 5-nm vertical field-effect transistors, IEEE Trans. Electron. Dev. 66 (1) (2018) 806-809.
  24. Jungmin Hong, et al., Alpha particle effect on multi-nanosheet tunneling field-effect transistor at 3-nm technology node, Micromachines 10 (12) (2019) 847.
  25. M. Pocaterra, et al., A unified model for TCAD simulation of the charge generated in semiconductors by low-energy alpha particles and protons, Microelectron. Reliab. 138 (2022) 114725.