반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
권호 표지

퍼시스턴트 메모리를 위한 저전력 캐시 플러싱 명령어 구현에 대한 연구

A Study on the Implementation of Low-Power Cache Flushing Instructions for Persistent Memory

  • 최주희 (상명대학교 스마트정보통신공학과)
  • Juhee Choi (Dept. of Smart Information Communication Engineering, Sangmyung University)
  • 투고 : 2024.08.06
  • 심사 : 2024.09.12
  • 발행 : 2024.09.30
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초록

Persistent memory technology has been recognized as a next-generation memory solution because of its stability over traditional volatile memory. The primary advantage of persistent memory is its non-volatile nature, allowing data retention even when the power is off. Additionally, persistent memory offers faster read speeds compared to traditional HDDs and SSDs. However, ensuring data consistency through cache flushing commands is increasingly important so that performance and power consumption issue would be challenges. This paper proposes a new cache structure to mitigate the drawbacks of cache flushing by considering the number of flushes per cache line. On top of that, a counter and decision bit to track and manage these actions are added. As a result, this architecture decreases approximately 56% of the additional memory access.

키워드

과제정보

본 연구는 2024학년도 상명대학교 교내연구비를 지원받아 수행하였음(2024-A000-0369).

참고문헌

  1. Pelley, Steven, Peter M. Chen, and Thomas F. Wenisch, "Memory persistency," ACM SIGARCH Computer Architecture News, vol. 42, no. 3, pp. 265-276, 2014. https://doi.org/10.1145/2678373.2665712
  2. Wang, K. L., J. G. Alzate, and P. Khalili Amiri, "Lowpower non-volatile spintronic memory: STT-RAM and beyond," Journal of Physics D: Applied Physics, vol. 46, no. 7, pp. 074003, 2013.
  3. Wong, H-S. Philip, et al., "Phase change memory," Proceedings of the IEEE, vol. 98, no. 12, pp 2201-2227, 2010. https://doi.org/10.1109/JPROC.2010.2070050
  4. Mikolajick, Thomas, et al., "FeRAM technology for high density applications," Microelectronics Reliability, vol. 41, no. 7, pp 947-950, 2001. https://doi.org/10.1016/S0026-2714(01)00049-X
  5. Handy, Jim, and Tom Coughlin, "Optane's dead: Now what?," Computer, vol. 56, no .3, pp. 125-130, 2023. https://doi.org/10.1109/MC.2023.3235096
  6. Desnoyers, Peter, et al., "Persistent memory research in the post-optane era," Proceedings of the 1st Workshop on Disruptive Memory Systems, pp. 23-30, 2023.
  7. Wu, Kai, et al., "Ribbon: High performance cache line flushing for persistent memory," Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques, pp. 427-439, 2020.
  8. Li, Tuo, and Sri Parameswaran, "FaSe: fast selective flushing to mitigate contention-based cache timing attacks," Proceedings of the 59th ACM/IEEE Design Automation Conference, pp. 541-546, 2022.
  9. Lim, Soojung, and Hyokyung Bahn. "Selective flushing of modified data for smartphone buffer cache management." 2021 IEEE Asia-Pacific Conference on Computer Science and Data Engineering (CSDE), pp. 1-6, 2021.
  10. Jang, Minwoo, et al., "Defending against flush+ reload attack with DRAM cache by bypassing shared SRAM cache," IEEE Access, no. 8, pp. 179837-179844, 2020.
  11. Anand, Shashank, et al., "Skip It: Take Control of Your Cache!," Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, vol 2, pp. 1077- 1094, 2024.
  12. Hennessy, John L., and David A. Patterson, "Computer architecture: a quantitative approach." Elsevier, 2011.
  13. Sharafeddine, Mageda, Komal Jothi, and Haitham Akkary, "Disjoint out-of-order execution processor," ACM Transactions on Architecture and Code Optimization (TACO), vol. 9, no .3, pp. 1-32, 2012.
  14. J. Power, J. Hestness, M. S. Orr, M. D. Hill, and D. A. Wood, "gem5-gpu: A heterogeneous cpu-gpu simulator," IEEE Computer Architecture Letters, vol. 14, no. 1, pp. 34-36, 2015. https://doi.org/10.1109/LCA.2014.2299539
  15. Mahar, Suyash, et al., "Write Prediction for Persistent Memory Systems," 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 242-257, 2021.
  16. Intel, "Persistent memory programming," https://pmem.io
  17. Liu, Sihang, et al., "Janus: Optimizing memory and storage support for non-volatile memory systems," Proceedings of the 46th International Symposium on Computer Architecture, pp. 143-156, 2019.