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Time Reduction for Package Warpage Optimization based on Deep Neural Network and Bayesian Optimization

심층신경망 및 베이지안 최적화 기반 패키지 휨 최적화 시간 단축

  • Jungeon Lee (Departement of Industrial Engineering, Sungkyunkwan University) ;
  • Daeil Kwon (Departement of Industrial Engineering, Sungkyunkwan University)
  • 이중언 (성균관대학교 산업공학과) ;
  • 권대일 (성균관대학교 산업공학과)
  • Received : 2024.08.23
  • Accepted : 2024.09.30
  • Published : 2024.09.30

Abstract

Recently, applying a machine learning to surrogate modeling for rapid optimization of complex designs have been widely researched. Once trained, the machine learning surrogate model can predict similar outputs to Finite Element Analysis (FEA) simulations but require significantly less computing resources. In addition, combined with optimization methodologies, it can identify optimal design variable with less time requirement compared to iterative simulation. This study proposes a Deep Neural Network (DNN) model with Bayesian Optimization (BO) approach for efficiently searching the optimal design variables to minimize the warpage of electronic package. The DNN model was trained by using design variable-warpage dataset from FEA simulation, and the Bayesian optimization was applied to find the optimal design variables which minimizing the warpage. The suggested DNN + BO model shows over 99% consistency compared to actual simulation results, while only require 15 second to identify optimal design variable, which reducing the optimization time by more than 57% compared to FEA simulation.

최근 대리 모델에 머신 러닝 기술을 접목하여 복잡한 설계에 대한 최적화를 빠르게 달성하는 방법론이 활발히 연구되고 있다. 훈련된 머신 러닝 대리 모델은 복잡한 유한요소해석 시뮬레이션 대비 컴퓨팅 자원을 적게 소모하면서 동일한 해석 결과를 출력할 수 있다. 또한 훈련된 모델에 최적화를 결합하면 반복 시뮬레이션 대비 더 빠르게 최적의 설계 변수를 도출할 수 있다. 본 연구에서는 패키지 휨을 최소화하는 설계 변수 조합을 효과적으로 탐색하기 위하여 심층신경망과 베이지안 최적화를 적용하였다. 심층신경망 모델은 유한요소해석 시뮬레이션으로 획득한 설계 변수-휨 데이터셋을 바탕으로 훈련하였고, 해당 모델에 베이지안 최적화를 적용하여 휨을 최소화하는 최적의 설계 변수를 탐색하였다. 구축한 심층신경망 및 베이지안 최적화 모델은 실제 시뮬레이션 결과와 99% 이상 일치하는 동시에, 최적 설계 변수 탐색에 소요되는 시간은 15초에 불과하여, 1회의 시뮬레이션과 비교해도 57% 이상 최적화 시간을 단축할 수 있다.

Keywords

Acknowledgement

이 성과는 정부 (과학기술정보통신부)의 재원으로 한국연구재단의 지원 (No. RS-2023-00239657), (No. 2022R1F1A1069114), (No. RS-2024-00423772) 및 SEMES의 재원으로 SEMES-성균관대 전략산학 과제의 지원을 받아 수행된 연구임 (S-2023-2065-000, 차세대 반도체 공정 장비 기술개발)

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