Acknowledgement
This work is partially supported by SR University, Warangal, Telangana, India (Dept. of Electronics and Communication Engineering).
References
- F. Farha, H. Ning, K. Ali, L. Chen, and C. Nugent, SRAMPUF-based entities authentication scheme for resource-constrained IoT devices, IEEE Internet Things J. 8 (2021), no. 7, 5904-5913. https://doi.org/10.1109/JIOT.2020.3032518
- C. J. Jhang, C. X. Xue, J. M. Hung, F. C. Chang, and M. F. Chang, Challenges, and trends of SRAM-based computing-in-memory for AI edge devices, IEEE trans, Circuits Syst. I: Regul. Pap. 68 (2021), no. 5, 1773-1786. https://doi.org/10.1109/TCSI.2021.3064189
- J. W. Su, X. Si, Y. C. Chou, T. W. Chang, W. H. Huang, Y. N. Tu, R. Liu, P. J. Lu, T. W. Liu, J. H. Wang, Y. L. Chung, J. S. Ren, F. C. Chang, Y. Wu, H. Jiang, S. Huang, S. H. Li, S. S. Sheu, C. I. Wu, C. C. Lo, R. S. Liu, C. C. Hsieh, K. T. Tang, S. Yu, and M. F. Chang, Two-way transpose multibit 6T SRAM computing-in-memory macro for inference-training AI edge chips, IEEE J. Solid-State Circuits. 57 (2022), no. 2, 609-624. https://doi.org/10.1109/JSSC.2021.3108344
- F. Shen, C. Xu, and J. Zhang, Statistical behavior guided block allocation in hybrid cache-based edge computing for cyber-physical-social systems, IEEE Access. 8 (2020), 29055-29063. https://doi.org/10.1109/ACCESS.2020.2972305
- Y. C. Chien and J. S. Wang, A 0.2 V 32-kb 10T SRAM with 41 nW standby power for IoT applications, IEEE Trans. Circuits Syst. I: Regul. Pap. 65 (2018), no. 8, 2443-2454. https://doi.org/10.1109/TCSI.2018.2792428
- V. Sharma, S. Vishvakarma, S. S. Chouhan, and K. Halonen, A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes, ETRI J. 46 (2018), 2314-2333.
- Q. Liu, K. Fujiwara, X. Meng, S. R. Whiteley, T. van Duzer, N. Yoshikawa, Y. Thakahashi, T. Hikida, and N. Kawai, Latency and power measurements on a 64-kb hybrid Josephson-CMOS memory, IEEE Trans. Appl. Supercond. 17 (2007), no. 2, 526-529. https://doi.org/10.1109/TASC.2007.898698
- K. S. Venkataraman, G. Dong, and T. Zhang, Techniques mitigating update-induced latency overhead in shingled magnetic recording, IEEE Trans. Magn. 48 (2012), no. 5, 1899-1905. https://doi.org/10.1109/TMAG.2011.2178099
- K. V. Noren and M. Meng, Macro-model development for a FLOTOX EEPROM, IEEE Trans. Electron. Devices. 45 (1998), no. 1, 224-229. https://doi.org/10.1109/16.658835
- L. Z. Scheick, P. J. McNulty, and D. R. Roth, Measurement of the effective sensitive volume of FAMOS cells of an ultraviolet erasable programmable read-only memory, IEEE Trans. Nucl. Sci. 47 (2000), no. 6, 2428-2434. https://doi.org/10.1109/23.903788
- Y. Ouyang, Z. Xia, T. Yang, D. Shi, W. Zhou, and Z. Huo, Optimization of performance and reliability in 3D NAND flash memory, IEEE Electron Device Lett. 41 (2020), no. 6, 840-843. https://doi.org/10.1109/LED.2020.2987087
- W. H. Lee, D. K. Lee, K. S. Kim, K. O. Ahn, and K. D. Suh, Mobile ion-induced data retention failure in NOR flash memory cell, IEEE Trans. Device Mater. Reliab. 1 (2001), no. 2, 128-132. https://doi.org/10.1109/7298.956707
- T. Douseki and Y. Ohmori, BiCMOS circuit technology for a high-speed SRAM, IEEE J. Solid-State Circuits. 23 (1988), no. 1, 68-73. https://doi.org/10.1109/4.258
- J. Lee, S. Jeon, and S. K. Chang, Effect of shield line on noise margin and refresh time of planar DRAM cell for embedded application, ETRI J. 26 (2004), no. 6, 583-588. https://doi.org/10.4218/etrij.04.0103.0140
- J. Kim, M. Lee, Y. Song, and Y. I. Eom, DJFS: Providing highly reliable and high-performance file system with small-sized NVRAM, ETRI J. 39 (2017), no. 6, 820-831. https://doi.org/10.4218/etrij.17.0117.0558
- R. Rajaei and S. B. Mamaghani, A nonvolatile, low-power, and highly reliable MRAM block for advanced microarchitectures, IEEE Trans. Device Mater. Reliab. 17 (2017), no. 2, 472-474. https://doi.org/10.1109/TDMR.2017.2694228
- X. Fong and K. Roy, Complimentary polarizers STT-MRAM (CPSTT) for on-chip caches, IEEE Electron. Device Lett. 34 (2013), no. 2, 232-234. https://doi.org/10.1109/LED.2012.2234079
- H. Koike, K. Amanuma, T. Miwa, J. Yamada, and H. Toyoshima, FeRAM retention analysis method based on memory cell read signal voltage measurement, IEEE Trans. Semi. Manuf. 15 (2002), no. 2, 201-208. https://doi.org/10.1109/66.999593
- S. Kawashima, T. Endo, A. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita, and M. Aoki, Bitline GND sensing technique for low-voltage operation FeRAM, IEEE J. Solid-State Circuits 37 (2002), no. 5, 592-598. https://doi.org/10.1109/4.997852
- Y. Chung and S. W. Shim, An experimental 0.8 V 256-kbit SRAM macro with boosted cell array scheme, ETRI J. 29 (2007), no. 4, 457-462. https://doi.org/10.4218/etrij.07.0106.0298
- J. P. Son, H. G. Byun, Y. H. Jun, K. Kim, and S. W. Kim, Temperature-adaptive back-bias voltage generator for an RCAT pseudo SRAM, ETRI J. 32 (2010), no. 3, 406-413. https://doi.org/10.4218/etrij.10.0109.0366
- A. Naeemi and J. D. Meindl, Compact physics-based circuit model for GNR interconnect, IEEE Trans. Electron. Devices 56 (2009), no. 9, 1822-1833. https://doi.org/10.1109/TED.2009.2026122
- X. Chuan, L. Hong, and K. Banerjee, Modeling, analysis, and design of graphene nano-ribbon interconnects, IEEE Trans. Electron Device 56 (2009), no. 8, 1567-1578. https://doi.org/10.1109/TED.2009.2024254
- R. Murali, K. Brenner, Y. Yang, T. Beck, and J. D. Meindl, Resistivity of graphene nanoribbon interconnects, IEEE Electron. Device Lett. 30 (2009), no. 6, 611-613. https://doi.org/10.1109/LED.2009.2020182
- S. H. Nasiri, M. K. M. Farshi, and R. Faez, Stability analysis in graphene nanoribbon interconnects, IEEE Electron. Device Lett. 31 (2010), no. 12, 1458-1460. https://doi.org/10.1109/LED.2010.2079312
- S. Bhattacharya, D. Das, and H. Rahaman, Reduced thickness interconnect model using GNR to avoid crosstalk effects, J. Comput. Electron. 15 (2016), no. 2, 367-380. https://doi.org/10.1007/s10825-016-0794-5
- S. Bhattacharya, S. das, A. Mukhopadhyay, D. das, and H. Rahaman, Analysis of a temperature-dependent delay optimization model for GNR interconnects using a wire sizing method, J. Comput. Electron. 17 (2018), no. 4, 1536-1548. https://doi.org/10.1007/s10825-018-1251-4
- A. K. Nishad and R. Sharma, Analytical time-domain models for performance optimization of multilayer GNR interconnects, IEEE J. Sel. Top. Quantum Electron. 20 (2014), no. 1, 17-24.
- S. Bhattacharya, D. Das, and H. Rahaman, Stability analysis in top contact and side-contact graphene nanoribbon interconnects, IETE J. Res. 63 (2017), no. 4, 588-596. https://doi.org/10.1080/03772063.2017.1292155
- S. Bhattacharya, D. Das, and H. Rahaman, Analysis of simultaneous switching noise and IR-drop in side-contact multilayer graphene nanoribbon power distribution network, J. Circuit Syst. Comput 27 (2017), no. 1, 1850001-1850017.
- S. Das, S. Bhattacharya, D. das, and H. Rahaman, Modeling and analysis of electro-thermal impact of crosstalk induced gate oxide reliability in pristine and intercalation doped MLGNR interconnects, IEEE Trans. Device Mater. Reliab. 19 (2019), no. 3, 543-550. https://doi.org/10.1109/TDMR.2019.2933035
- S. Bhattacharya, D. Das, and H. Rahaman, Analysis of delay fault in GNR power interconnects, Int. J. Numer. Model. 31 (2017), no. 3, e2380.
- S. Bhattacharya, D. Das, and H. Rahaman, Modeling and performance analysis of graphene nanoribbon interconnects, Natl. Acad. Sci. Lett. 40 (2017), no. 2017, 325-329. https://doi.org/10.1007/s40009-017-0572-3