DOI QR코드

DOI QR Code

Multi-Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

  • Mohammad Ali Bandari (Department of Electrical Engineering, Islamic Azad University) ;
  • Mohammad Bagher Tavakoli (Department of Electrical Engineering, Islamic Azad University) ;
  • Farbod Setoudeh (Department of Electrical Engineering, Arak University of Technology) ;
  • Massoud Dousti (Department of Electrical and Computer, Engineering, Science and Research Branch, Islamic Azad University)
  • 투고 : 2022.03.11
  • 심사 : 2022.07.27
  • 발행 : 2023.08.10

초록

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 ㎛. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 ㎼.

키워드

참고문헌

  1. A. D. Grasso, G. Palumbo, and S. Pennisi, Analytical comparison of frequency compensation techniques in three-stage amplifiers, Int. J. Circuit. Theor. Appl. 36 (2008), no. 1, 53-80. https://doi.org/10.1002/cta.397
  2. X. Peng and W. Sansen, AC boosting compensation scheme for low-power multi-stage amplifiers, IEEE J. Solid State Circuits 39 (2004), no. 11, 2074-2079. https://doi.org/10.1109/JSSC.2004.835811
  3. M. Akbari, S. Biabanifard, S. Asadi, and M. C. E. Yagoub, High performance folded cascode OTA using positive feedback and recycling structure, Analog. Integr. Circuits. Signal. Process. 82 (2015), 217-227. https://doi.org/10.1007/s10470-014-0464-0
  4. A. D. Grasso, D. Marano, G. Palumbo, and S. Pennisi, Analytical comparison of reversed nested Miller frequency compensation techniques, Int. J. Circuit Theor. Appl. 38 (2010), no. 7, 709-737. https://doi.org/10.1002/cta.600
  5. A. D. Grasso, G. Palumbo, and S. Pennisi, Advances in reversed nested Miller compensation, IEEE Trans. Circuits Syst. I. 54 (2007), no. 7, 1459-1470. https://doi.org/10.1109/TCSI.2007.900170
  6. S. Biabanifard, S. M. Largani, A. Biamanifard, M. Biabanifard, M. Hemmati, and Z. Khanmohammadi, Three stages CMOS operational amplifier frequency compensation using single Miller capacitor and differential feedback path, Analog. Integr. Circuits. Signal Process. 97 (2018), no. 2, 195-205. https://doi.org/10.1007/s10470-018-1117-5
  7. S. Biabanifard, S. Mehdi Largani, M. Akbari, S. Asadi, and M. C. E. Yagoub, High performance reversed nested Miller frequency compensation, Analog Integr. Circuits Signal Process. 85 (2015), no. 1, 223-233. https://doi.org/10.1007/s10470-015-0616-x
  8. M. Soltani Zanjani, T. Asiyabi, and S. Biabanifard, A high-performance CMOS four-stage amplifier, Int. J. Numer. Model.: Electron. Netw. Devices Fields. 32 (2019), no. 6, e2647.
  9. S. Biabanifard, S. M. Hosseini, M. Biabanifard, S. Asadi, and M. C. E. Yagoub, Multi stage OTA design: From matrix description to circuit realization, Microelectron J. 77 (2018), 49-65. https://doi.org/10.1016/j.mejo.2018.05.007
  10. A. D. Grasso, G. Palumbo, and S. Pennisi, High-performance four-stage CMOS OTA suitable for large capacitive loads, IEEE Trans. Circuits Syst. I. 62 (2015), no. 10, 2476-2484.
  11. M. Akbari, S. Biabanifard, S. Asadi, and M. C. E. Yagoub, Design and analysis of DC gain and transconductance boosted recycling folded cascode OTA, AEU - Int. J. Electron. Commun. 68 (2014), no. 11, 1047-1052. https://doi.org/10.1016/j.aeue.2014.05.007
  12. M. Akbari, S. Biabanifard, and S. Asadi, Input referred noise reduction technique for trans-conductance amplifiers, Int. J. Electr. Comput. Eng. (ECIJ). 4 (2015), no. 4, 11-22.
  13. M. Zaherfekr and A. Biabanifard, Improved reversed nested miller frequency compensation technique based on current comparator for three-stage amplifiers, Analog Integr. Circuits Signal Process. 98 (2019), no. 3, 633-642. https://doi.org/10.1007/s10470-019-01405-1
  14. D. Marano, A. D. Grasso, G. Palumbo, and S. Pennisi, Optimized active single-Miller capacitor compensation with inner half-feedforward stage for very high-load three-stage OTAs, IEEE Trans. Circuits Syst. I. 63 (2016), no. 9, 1349-1359. https://doi.org/10.1109/TCSI.2016.2573920
  15. T. Asiyabi, M. S. Zanjani, M. Goodarzi, and S. Biabanifard, Four stage OTA CMOS frequency compensation based on double differential feedback paths, Analog. Integr. Circuits. Signal Process. 101 (2019), no. 1, 155-168. https://doi.org/10.1007/s10470-019-01515-w
  16. M. A. Bandari, F. Setoudeh, M. B. Tavakoli, and M. Dousti, Three-stage CMOS amplifier: frequency compensated using fully differential block, Int. J. Numer. Modell Electron Netw. Devices Fields 35 (2022), no. 5, e3007.
  17. H. Aminzadeh and M. A. Dashti, Dual loop cascode-Miller compensation with damping factor control unit for three-stage amplifiers driving ultralarge load capacitors, Int. J. Circuit Theor. Appl. 47 (2019), no. 1, 1-18. https://doi.org/10.1002/cta.2563
  18. A. K. N. Leung, P. K. T. Mok, W. H. Ki, and J. K. O. Sin, Damping-factor-control frequency compensation technique for low-voltage low-power large capacitive load applications, (IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC, San Francisco, CA, USA), Feb. 1999. https://doi.org/10.1109/ISSCC.1999.759173
  19. W. Aloisi, G. Palumbo, and S. Pennisi, Design methodology of Miller frequency compensation with current buffer/amplifier, IET Circuits Devices Syst. 2 (2008), no. 2, 227-233. https://doi.org/10.1049/iet-cds:20060188
  20. S. Guo and H. Lee, Dual active-capacitive-feedback compensation for low-power large-capacitive-load three-stage amplifiers, IEEE J. Solid State Circuits 46 (2010), no. 2, 452-464.
  21. S. Zanjani, F. K. Masoud, and S. J. Seyyed Mahdavi Chabok, Multi-stage operational transconductance amplifier frequency compensation technique based on fully differential feedback stage, Int. J. Numer. Modell Electron Netw. Devices Fields 33 (2020), no. 2, e2702.
  22. S. M. Hosseini Largani, S. Shahsavari, S. Biabanifard, and A. Jalali, A new frequency compensation technique for three stages OTA by differential feedback path, Int. J. Numer Modell Electron Netw. Devices Fields 28 (2015), no. 4, 381-388. https://doi.org/10.1002/jnm.2013
  23. S. Shahsavari, S. Biabanifard, S. M. Hosseini Largani, and O. Hashemipour, DCCII based frequency compensation method for three stage amplifiers, AEU Int. J. Electron. Commun. 69 (2015), no. 1, 176-181. https://doi.org/10.1016/j.aeue.2014.08.011
  24. G. Giustolisi and G. Palumbo, Design of CMOS three-stage amplifiers for near-to-minimum settling-time, Microelectron J. 107 (2021), 104939.
  25. A. R. Loera, A. Veerabathini, L. A. F. Oropeza, L. A. C. Martinez, and D. M. Frias, Improved frequency compensation technique for three-stage amplifiers, J. Low Power Electron. Appl. 11 (2021), 11.
  26. T. Asiyabi and J. Torfifard, Differential block frequency compensation for low-power multi-stage amplifiers, Int. J. Numer. Modell. Electron. Netw. Devices Fields 32 (2019), no. 1, e2517.
  27. M. A. Mohammed and G. W. Roberts, Generalized relationship between frequency response and settling time of CMOS OTAs: toward many-stage design, IEEE Trans. Circuits Syst. I. 68 (2021), no. 12, 4993-5006. https://doi.org/10.1109/TCSI.2021.3110106
  28. H. Aminzadeh, A. D. Grasso, and G. Palumbo, A methodology to derive a symbolic transfer function for multistage amplifiers, IEEE Access 10 (2022), 14062-14075. https://doi.org/10.1109/ACCESS.2022.3147879
  29. H. Aminzadeh, Systematic circuit design and analysis using generalised gm/ID functions of MOS devices, IET Circuits Devices Syst. 14 (2020), no. 4, 432-443. https://doi.org/10.1049/iet-cds.2019.0209