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PVT 변화 보상 기능을 가지는 시간-디지털 변환기

A Time-to-Digital Converter with PVT Variation Compensation Capability

  • Eunho Shin (Dept. of Electronic & Electrical Engineering, Hongik University) ;
  • Jongsun Kim (Dept. of Electronic & Electrical Engineering, Hongik University)
  • 투고 : 2023.08.18
  • 심사 : 2023.09.18
  • 발행 : 2023.09.30

초록

본 논문에서는 PVT(process, voltage, and temperature) 변화에 대한 보상기능을 가지는 시간-디지털 변환기(time-to-digital converter : TDC)를 제안한다. 일반적인 지연 라인(delay line) 기반의 TDC는 인버터의 전파 지연을 기반으로 시간을 측정하기 때문에 근본적으로 PVT 변화에 민감하다. 이 논문은 PVT 변화에 의한 전파 지연을 보상하여 TDC의 해상도 변화를 최소화시키는 방법을 제안한다. 또한 넓은 입력 측정 범위(detection range)를 갖기 위해 Cyclic Vernier TDC (CVTDC) 구조를 채택한다. 제안하는 PVT보상 기능의 CVTDC는 45nm CMOS 공정으로 설계되어, 8mW의 전력을 소모하며, 5 ps의 TDC 해상도 및 약 5.1 ns 입력 측정 범위를 갖는다.

In this paper, we propose a time-to-digital converter (TDC) with compensation capability for PVT (process, voltage, and temperature) variations. A typical delay line-based TDC measures time based on the inverter's propagation delay, making it fundamentally sensitive to PVT variations. This paper presents a method to minimize the resolution change of TDC by compensating for the propagation delay caused by the PVT variations. Additionally, it dopts Cyclic Vernier TDC (CVTDC) structure to provide a wide input detection range. The proposed CVTDC with PVT compensation function is designed using a 45nm CMOS process, consumes 8mW of power, offers a TDC resolution of 5 ps, and has an input detection range of about 5.1 ns.

키워드

과제정보

This work was supported by Korea Institute for Advancement of Technology (KIAT) grant funded by the Korea Government (MOTIE) P0020966. This work was also supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2022M3I8A107243). The EDA tools were supported by IDEC.

참고문헌

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