반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
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반도체 테스트 비용 절감을 위한 랜덤 테스트 효율성 향상 기법

A Method on Improving the Efficiency of Random Testing for VLSI Test Cost Reduction

  • 이성제 (호서대학교 전자공학과) ;
  • 이상석 (호서대학교 전자공학과) ;
  • 안진호 (호서대학교 전자공학과)
  • Sungjae Lee (Hoseo University, Department of Electronic Engineering) ;
  • Sangseok Lee (Hoseo University, Department of Electronic Engineering) ;
  • Jin-Ho Ahn (Hoseo University, Department of Electronic Engineering)
  • 투고 : 2023.02.27
  • 심사 : 2023.03.16
  • 발행 : 2023.03.31
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초록

In this paper, we propose an antirandom pattern-based test method considering power consumption to compensate for the problem that the fault coverage through random test decreases or the test time increases significantly when the DUT circuit structure is complex or large. In the proposed method, a group unit test pattern generation process and rearrangement process are added to improve the problems of long calculation time and high-power consumption, which are disadvantages of the previous antirandom test.

키워드

과제정보

이 논문은 2022년도 호서대학교의 재원으로 학술연구비 지원을 받아 수행된 연구임(202202070001).

참고문헌

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