A Single-Bit 3rd-Order Feedforward Delta Sigma Modulator Using Class-C Inverters for Low Power Audio Applications

저전력 오디오 응용을 위한 Class-C 인버터 사용 단일 비트 3차 피드포워드 델타 시그마 모듈레이터

Abstract

In this paper, a single-bit 3rd-order feedforward delta sigma modulator is proposed for audio applications. The proposed modulator is based on a class-C inverter for low voltage and power applications. For the high-precision requirement, the class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier. The proposed Class-C inverter-based modulator is designed and simulated in 180-nm CMOS process. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based switched-capacitor modulator achieves high power efficiency. This design achieves an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply.

본 논문에서는 오디오 애플리케이션을 위한 단일 비트 3차 피드포워드 델타 시그마 변조기를 제안한다. 제안된 변조기는 저전압 및 저전력 애플리케이션을 위한 클래스-C 인버터를 기반으로 한다. 고정밀 요구 사항을 위해 레귤레이티드 캐스코드 구조의 클래스-C 인버터는 DC 이득을 증가시키고 저전압 서브쓰레스홀드 증폭기 역할을 한다. 제안된 클래스-C 인버터 기반 변조기는 180nm CMOS 공정으로 설계 및 시뮬레이션되었다. 성능 손실이 없으면서 낮은 공급 전압 호환성을 가지도록 제안된 클래스-C 인버터 기반 스위치드 커패시터 변조기는 높은 전력 효율을 달성하였다. 본 설계는 20kHz의 신호 대역폭 및 4MHz의 샘플링 주파수에서 동작시켜 93.9dB의 SNDR, 108dB의 SNR, 102dB의 SFDR 및 102dB의 DR를 달성하면서 0.8V 전원 전압에서 280μW의 전력 소비만 사용한다.

1. Introduction

As the market for smart phones, tablets, and wearable devices grows, so does demand for high-performance audio codecs. Newer technologies like virtual reality improve audio quality. The slow growth of battery capacity continues to hinder mobile audio use. Thus, optimizing the power consumption of delta sigma ADCs, the ideal candidate for audio ADCs due to their performance, is crucial without compromising linearity.

Optimizing the power-efficiency of a operational transconductance amplifiers (OTA) in the loop filter is the most effective approach to lower the power consumption of a delta sigma modulator [1]. The OTA design is a critical bottleneck in low-voltage analog circuits. Low voltage OTAs have been studied in [2–4], but their supply voltages are limited by the input common-mode voltage. To achieve optimum power efficiency, logic inverters have been proposed as an alternative to an OTA, resulting in inverter-based delta sigma modulators [5-7]. In inverters, NMOS and PMOS devices contribute to the overall transconductance gm with a single current source. This enables class-AB (or C) operation with fast slew rate, which maximizes power efficiency by compressing the quiescent current.

In this paper, we present a low power single-bit 3rd-order feedforward delta sigma modulator using class-C inverters for low power audio applications [8]. The class-C inverter-based switched capacitor (SC) integrators are placed into the single-bit 3rd-order feedforward audio modulator. In 180-nm CMOS technology, a prototype of the modulator is designed and simulated. This work obtains an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V supply.

2. Proposed Single-Bit 3rd-Order Feedforward Delta Sigma Modulator

2.1 Inverter-Based SC Integrator

As demonstrated in Fig. 1, an inverter can be utilized in place of an OTA as an amplifier inside the SC integrator [5]. The inverter functions as a class-C amplifier when the power supply voltage is less than the sum of the threshold voltages of the NMOS and PMOS. By auto-zeroing techniques [9], the offset voltage of the inverter, V_OFF which is uncertain and subject to the transistor size, threshold voltage, power supply voltage, and process variation can be reduced, the low frequency power noise and amplifier noise can be suppressed and the virtual ground is created. The inverter is switched to a configuration of unity gain, and V_OFF is sampled in C_C during the Φ₁ phase. Simultaneously, the v_I is sampled into C_S relative to the signal ground. The V_X should be V_OFF owing to C_I-formed negative feedback during the Φ₂ phase. This makes V_G the signal ground since C_C retains V_OFF. Consequently, the node VG can be viewed as a virtual ground, and then the charge in C_S must be transferred into C_I in a manner similar to that of a conventional SC integrator. As soon as the charge transfer is finished, the input node voltage of the inverter recovers to V_OFF, and the transistors inside the inverter once again function in the weak inversion region. Consequently, a high slew rate is attained with little static current since only one essential transistor is totally switched on the other one is completely turned off during the Φ₁ and Φ₂ transition and then all the transistors are in the weak inversion region in the steady-state of Φ₂. Implementing a pseudo-differential SC integrator improves noise immunity and reduces nonlinearity. The common-mode feedback (CMFB) capacitors (C_M) are drained to the signal ground at Φ₁ and create a CM voltage detector at Φ₂. The difference voltage between the detected CM voltage and signal ground is sent to the SC integrator that implements the CMFB loop, whose gain is determined by the ratio C_M/C_I.

Fig. 1. Inverter-based SC integrator (a) single-ended (b) pseudo-differential [5]

2.2 Architecture and Behavioral Simulation

For the full feedforward delta sigma modulator, as the internal nodes are just a function of quantization noise, irrespective of the input signal magnitude, the specifications such as the amplifier’s output swing and DC gain are relaxed [10]. This property makes the feedforward topology acceptable for delta sigma modulators with constrained amplifier performance. Since the single-bit delta sigma modulator has a comparator and a linear DAC, it is simpler than the multi-bit delta sigma modulator, decreasing the overall circuit’s complexity and having the power and area efficiency. Moreover, the single-bit topology has the benefit of limiting the non-ideal features of the integrator's amplifiers, switches, and capacitors [11]. Therefore, the proposed single-bit 3rd-order feedforward delta sigma modulator architecture is employed as depicted in Fig. 2.

Fig. 2. Block diagram of the proposed single-bit 3rd-order feedforward delta sigma modulator

The noise transfer function (NTF) is primarily designed with loop stability and in-band noise reduction. It is essential to guarantee that the maximum gain attained by NTF across all frequencies is less than 1.5 to make a single-bit modulator stable [12]. In order to decrease the noise power of the signal band and increase the output SNR, the RMS gain of the NTF must be optimized to be as little as feasible within the signal bandwidth. From the NTF optimization, the coefficients of the loop are determined as shown in Table 1, which results in an SNDR of 96.63 dB and a DR of 105 dB with a oversampling ratio (OSR) of 100 as shown in Fig. 3. On the other hand, when NTF optimization is not performed, it can be seen that the modulator has 95.91 dB SNDR and 102 dB DR.

Table 1. Coefficients of the loop in the proposed delta sigma modulator

Fig. 3. Output spectrum obtained by MATLAB behavioral simulation

The MATLAB behavioral simulation yields the histograms of the outputs of the first, second, and third integrators, which are depicted in Fig. 4. The histograms of the outputs of the first, second, and third integrators are kept within about 50.00%, 31.25%, and 18.75%, respectively, of the supply voltage of 0.8 V. Even when the input signal is raised by –6 dB relative to the supply voltage, these properties remain unchanged. Also, through the simulation, it is known that DC gains of 60 dB, 60 dB, and 40 dB are necessary for the first, second, and third integrators respectively to account for the amplifier's limited DC gain and its gain variations over the output swing.

Fig. 4. Histograms of the outputs of the first, second, and third integrators

2.3 Circuit Implementation

Fig. 5 depicts the proposed single-bit 3rd-order feedforward delta sigma modulator to obtain high resolution. Using the inverter-based integrators mentioned in Section 2.1, the loop filter of the delta sigma modulator is realized. The sampling capacitor of the first integrator, C_S1, has a value of 5 pF so as to achieve the desired thermal noise level. The offset-storage capacitor of the first integrator, C_C1, is selected to have a value of 12 pF, which is supposed to be large enough to prevent noise folding during the auto-zeroing phase. Thus, the input-referred noise of the first integrator, which is the primary noise source of the delta sigma modulator, is controlled to 5.8 μV_rms. The class-C inverter of the first integrator has the gain-bandwidth product (GBP) of 27.4 MHz and the slew rate of 13.6 V/μs while using 16 μA of static current. The sampling capacitors, C_S2 and C_S3, for the second and third integrators are scaled down to 1.0 pF and 0.3 pF, respectively. Therefore, the static currents of the second and third integrators are scaled down to 3.84 μA and 0.64 μA, respectively. Since in the case of the traditional cascode class-C inverter structure, it is not easy to design the DC gain to be more than 40dB, the class-C inverter with regulated cascode structure is used in the integrators [13]. The class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier.

For the addition of feedforward paths, a passive SC adder is utilized at the quantizer's input and a dynamic comparator is employed to create the single-bit quantizer [5]. The on-chip clock generator uses the 4 MHz master clock to create boosted, non-overlapping clock signals.

Fig. 5. Circuit diagram of the proposed single-bit 3rd-order feedforward delta sigma modulator​​​​​​​

3. Simulation Results

The proposed single-bit 3rd-order feedforward delta sigma modulator is designed and simulated in 180-nm CMOS process. The delta sigma modulator uses 0.8-V power supply voltage and has 280-μW power consumption.

Fig. 6 depicts the spectral response of the proposed single-bit 3rd-order feedforward delta sigma modulator achieved by the HSPICE simulation. When an OSR of 100 and an input signal of 2 kHz is applied for a 20 kHz bandwidth, the simulation result shows that the modulator with NTF optimization has 93.9-dB SNDR, 108-dB SNR, 102-dB SFDR, and 15.31-bit effective number of bits (ENOB), whereas the modulator without NTF optimization has 91.11-dB SNDR, 105-dB SNR, 100-dB SFDR, and 14.84-bit ENOB. When comparing the MATLAB simulation in Fig. 3 and the HSPICE simulation result in Fig. 6, it can be seen that the actual circuit result has a performance degradation of 2.73 dB for SNDR. This is because there is performance degradation due to the parasitic components in transistors and capacitors.

Fig. 6. Output spectrum obtained by HSPICE simulation​​​​​​​

Fig. 7 shows the simulated SNDR versus the amplitude of the input signal. A 0-dB input level corresponds to a sinusoidal input whose peak-to-peak differential voltage is 0.8 V. The delta sigma modulator has a DR of 102 dB.

The proposed modulator's performance summary and comparison with earlier works are shown in Table 2. The Schreier's Figure-of-Merit (FoM) with SNDR [5] is utilized for a fair comparison as

\(\begin{aligned}F_{O} M_{S N D R}=\frac{\text { Power }}{2^{(S N D R-1.76) / 6.02} \times 2 \times B W}\end{aligned}\)       (1)

Fig. 7. simulated SNDR versus the amplitude of the input signal​​​​​​​

Table 2. Modulator performance summary and comparison​​​​​​​

where a unit of FoM_SNDR is pJ/conversion-step. This work acheives 0.172-pJ/conversion-step FoM_SNDR. Although the proposed modulator has lager FoM_SNDR than the modulator in [5], the proposed modulator is more suitable for applications with higher SNR, SNDR and SFDR.

4. Conclusion

In this paper, we proposed the single-bit 3rd-order feedforward delta-sigma modulator for audio applications. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based SC modulator achieves high power efficiency. This work achieves an SNDR of 93.9 dB, an SNR of 108 dB, an SFDR of 102 dB, and a DR of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply. The inverter-based SC design features a wide application prospect in low-voltage, low-power, and high-performance ICs.