Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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A Study on Effect of Pad Design on Assembly and Adhesion Reliability of Surface Mount Technology (SMT)

표면실장기술(SMT)의 조립 및 접합 신뢰성에 대한 패드설계의 영향에 관한 연구

  • Park, Dong-Woon (Department of Mechanical Convergence Engineering, Hanyang University) ;
  • Yu, Myeong-Hyeon (Department of Mechanical Convergence Engineering, Hanyang University) ;
  • Kim, Hak-sung (Department of Mechanical Convergence Engineering, Hanyang University)
  • 박동운 (한양대학교 융합기계공학과) ;
  • 유명현 (한양대학교 융합기계공학과) ;
  • 김학성 (한양대학교 융합기계공학과)
  • Received : 2022.09.08
  • Accepted : 2022.09.30
  • Published : 2022.09.30
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Abstract

Recently, with the 4th industrial revolution, the demand for high-density semiconductors for large-capacity data processing is increasing. Researchers are interested in researching the reliability of surface mount technology (SMT). In this study, the effect of PCB pad design on assembly and adhesion reliability of passive component was analyzed using design of experiment (DOE). The DOE method was established using the pad length, width, and distance between pads of the PCB as variables. The assembly defect rate of the passive element after the reflow process was derived according to the misplacement direction of the chip resistor. The shear force between the passive element and the PCB was measured using shear tests. In addition, the shape of the solder according to the pad design was analyzed through cross-sectional analysis.

최근 4차산업혁명으로 대용량 데이터 처리를 위한 고집적 반도체에 대한 수요가 증가하고 있다. 반도체 제품에 장착되는 소자들의 크기가 작아 짐에 따라 표면실장기술(SMT)의 신뢰성에 대한 연구가 관심을 받고 있다. 본 연구에서는 PCB의 패드 디자인이 수동소자의 조립 및 접합 신뢰성에 미치는 영향을 실험 계획법(design of experiment, DOE) 이용하여 분석하였다. 수동소자를 실장하기 위한 PCB의 패드 길이, 너비 및 두 패드간 거리를 변수로 하여 실험계획법을 수립하였다. 저항칩의 오배치(misplacement) 방향에 따른 수동소자의 톰스톤(tombstone)불량률을 도출하였다. 전단테스트를 통해 수동소자와 PCB 사이의 전단력을 측정하였다. 또한, 단면분석을 통해 패드 디자인에 따른 솔더의 형상을 분석하였다.

Keywords

Acknowledgement

This research was also supported by a National Research Foundation of Korea (NRF) grant funded by the Korean Government (MEST) (2021M2E6A1084690)

References

  1. L. Bai, X. Yang, and H. Gao, "Corner point-based coarse-fine method for surface-mount component positioning", 14(3), 877-886 (2017).
  2. S. Yu, J. Sohn, S. Park, and B. J. Oh, "Efficient operation of a multi-functional surface mounting device", 33(3-4), 797- 800 (1997).
  3. C. Marques, N. Lopes, G. Santos, I. Delgado, and P. Delgado, "Improving operator evaluation skills for defect classification using training strategy supported by attribute agreement analysis", 119, 129-141 (2018).
  4. Y.-G. Kim and T.-H. Park, "SMT assembly inspection using dual-stream convolutional networks and two solder regions" 10(13), 4598 (2020).
  5. M.-H. C. Li, A. Al-Refaie, and C.-Y. Yang, "DMAIC approach to improve the capability of SMT solder printing process", 31(2), 126-133 (2008).
  6. C. Y. Huang, Y. H. Lin, K. C. Ying, and C. L. Ku, "The solder paste printing process: critical parameters, defect scenarios, specifications, and cost reduction", Soldering & Surface Mount Technology, 23(4), 211-223 (2011). https://doi.org/10.1108/09540911111169057
  7. M. Rusdi, M. Abdullah, M. Ishak, M. A. Aziz, M. Abdullah, P. Rethinasamy, and A. Jalar, "Three-dimensional CFD simulation of the stencil printing performance of solder paste", 108(9), 3351-3359 (2020).
  8. E. H. Amalu, Y. Lui, N. Ekere, R. Bhatti, and G. Takyi, "Investigation of The Effects of Reflow Profile Parameters on Lead-free Solder Bump Volumes And Joint Integrity", AIP Conference Proceedings, 639-644 (2011).
  9. N. C. Lee, "Optimizing the reflow profile via defect mechanism analysis", Soldering & Surface Mount Technology, 11(1), 13-20 (1999). https://doi.org/10.1108/09540919910254642
  10. D. Li, L. Wang, and Q. Huang, "A case study of SOS-SVR model for PCB throughput estimation in SMT production lines", 2019 International Conference on Industrial Engineering and Systems Management (IESM),-6(2019)
  11. W. H. Chen, K. N. Chiang, and S. R. Lin, "Prediction of liquid formation for solder and non-solder mask defined array packages", Journal of Electronic Packaging, 124(1), 37-44 (2002). https://doi.org/10.1115/1.1401738
  12. Y. Wang, M. Olorunyomi, M. Dahlberg, Z. Djurovic, J. Anderson, and J. Liu, "Process and pad design optimization for 01005 passive component surface mount assembly", Soldering & Surface Mount Technology, 19(1), 34-44 (2007). https://doi.org/10.1108/09540910710748212
  13. K. C. K. Chuan, S. Sutiono, B. Senthil, K. G. T. Tiam, K. S. Sig, R. S. Kumar, Z. R. Fen, and C. Li-San, "Voids Reduction in Fine Pitch SiP Assembly Through Optimization of Reflow Parameters", IEEE 22nd Electronics Packaging Technology Conference (EPTC), 291-296 (2020).
  14. M. Branzei, M. Vladescu, B. Mihailescu, L. Plotog, and G. Varzaru, "Investigations related to electrically conductive adhesives pastes usage on SMT lines", 2018 IEEE 24th International Symposium for Design and Technology in Electronic Packaging (SIITME), 355-360 (2018).