The Journal of the Korea institute of electronic communication sciences (한국전자통신학회논문지)

Korea Institute of Electronic Communication Science (한국전자통신학회)
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Approximate Multiplier with High Density, Low Power and High Speed using Efficient Partial Product Reduction

효율적인 부분 곱 감소를 이용한 고집적·저전력·고속 근사 곱셈기

  • Seo, Ho-Sung ;
  • Kim, Dae-Ik (School of Electrical, Electronic Communication, and Computer Engr., Chonnam National University)
  • 서호성 (전남대학교 전자통신공학과) ;
  • 김대익 (전남대학교 전기전자통신컴퓨터공학부)
  • Received : 2022.06.24
  • Accepted : 2022.08.17
  • Published : 2022.08.31
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Abstract

Approximate computing is an computational technique that is acceptable degree of inaccurate results of accurate results. Approximate multiplication is one of the approximate computing methods for high-performance and low-power computing. In this paper, we propose a high-density, low-power, and high-speed approximate multiplier using approximate 4-2 compressor and improved full adder. The approximate multiplier with approximate 4-2 compressor consists of three regions of the exact, approximate and constant correction regions, and we compared them by adjusting the size of region by applying an efficient partial product reduction. The proposed approximate multiplier was designed with Verilog HDL and was analyzed for area, power and delay time using Synopsys Design Compiler (DC) on a 25nm CMOS process. As a result of the experiment, the proposed multiplier reduced area by 10.47%, power by 26.11%, and delay time by 13% compared to the conventional approximate multiplier.

근사 컴퓨팅은 정확한 결과 대신에 허용 가능한 정도의 부정확한 결과를 도출하는 연산 기법이다. 근사 곱셈은 고성능, 저전력 컴퓨팅을 위한 근사 컴퓨팅 방식 중 하나이다. 본 논문에서는 근사 4-2 compressor와 향상된 전가산기를 사용하여 고집적·저전력·고속 근사 곱셈기를 제안하였다. 근사 4-2 compressor를 사용한 근사 곱셈기는 정확, 근사, 상수 수정 영역의 3개 영역으로 구성되어 있으며, 효율적인 부분 곱 감소 방식을 적용하여 각 영역의 크기를 조절하면서 성능을 비교하였다. 제안한 근사 곱셈기는 Verilog HDL로 설계하였고, 25nm CMOS 공정에서 Synopsys Design Compiler(DC)를 이용하여 면적, 전력, 지연시간을 분석하였으며, 기존의 근사 곱셈기에 비해 면적을 10.47%, 전력을 26.11%, 지연시간을 13% 줄였다.

Keywords

References

  1. S. Mittal, "A survey of techniques for approximate computing," ACM Comput. Surveys, vol. 48, no. 4, May 2016, pp. 1-33.
  2. S. Narayanamoorthy, H. A. Moghaddam, Z. Liu, T. Park, and N. Kim, "Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications," in Trans IEEE VLSI system, vol. 23, no. 6, June 2015, pp. 1180-1184. https://doi.org/10.1109/TVLSI.2014.2333366
  3. J. Han and M. Orshansky, "Approximate computing : An emerging paradigm for energy-efficient design," IEEE European Test Symposium(ETS), Avignon, France, May 2013, pp. 1-6.
  4. A. D. Booth, "A signed binary multiplication technique," The Quarterly Journal, vol. 4, no. 2, Jan. 1951, pp. 236-240.
  5. S. Nambi, U. A. Kumar, K. Radhakrishnan, M. Venkatesan, and S. E. Ahmed, "DeBAM : Decoder-Based Approximate Multiplier for Low Power Applications," IEEE Embedded Systems Letters, vol. 13, no. 4, Dec. 2021, pp. 174-177. https://doi.org/10.1109/LES.2020.3045165
  6. A. Weinberger, "4:2 Carry-Save Adder Module," IBM Technical Disclosure Bulletin, vol. 23, Jan. 1981, pp. 3811-3814.
  7. A. Momeni, J. Han, P. Montuschi, and F. Lombardi, "Design and Analysis of Approximate compressors for Multiplication," in Trans IEEE Comput. vol. 64, no. 5, Apr. 2015, pp. 984-994. https://doi.org/10.1109/TC.2014.2308214
  8. Z. Yang, J. Han, and F. Lombardi, "Approximate compressors for error-resilient multiplier design," IEEE DFTS, Oct. 2015, pp. 12-14.
  9. M. Ha and S. Lee, "Multipliers With Approximate 4-2 compressors and Error Recovery Modules," IEEE Embedded System Letters, vol. 10, no. 1, Mar. 2018, pp. 6-9. https://doi.org/10.1109/les.2017.2746084
  10. U. A. Kumar, S. K. Chatterjee, and S. E. Ahmed, "Low-Power compressor-based Approximate Multipliers with Error Correcting Module," IEEE Embedded System Letters, vol. 14, no. 2, June 2022, pp. 59-62. https://doi.org/10.1109/LES.2021.3113005
  11. S. Kim, H. Seo, Su. Kim, and D. Kim, "Approximate Multiplier with efficient 4-2 compressor and compensation characteristic," The Korea Institute of Electronic Communication Sciences, vol. 17, no. 1, Feb. 2022, pp. 173-180.
  12. P. Patali and S. T. Kassim, "An Efficient Architecture for Signed Carry Save Multiplication," IEEE Letters of the Computer Society, vol. 3, no. 1, Feb. 2020, pp. 9-12. https://doi.org/10.1109/locs.2020.2971443