Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Adaptive Processing Algorithm Allocation on OpenCL-based FPGA-GPU Hybrid Layer for Energy-Efficient Reconfigurable Acceleration of Abnormal ECG Diagnosis

비정상 ECG 진단의 에너지 효율적인 재구성 가능한 가속을 위한 OpenCL 기반 FPGA-GPU 혼합 계층 적응 처리 알고리즘 할당

  • Lee, Dongkyu (School of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Lee, Seungmin (School of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Park, Daejin (School of Electronic and Electrical Engineering, Kyungpook National University)
  • Received : 2021.08.19
  • Accepted : 2021.09.06
  • Published : 2021.10.31
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Abstract

The electrocardiogram (ECG) signal is a good indicator for early diagnosis of heart abnormalities. The ECG signal has a different reference normal signal for each person. And it requires lots of data to diagnosis. In this paper, we propose an adaptive OpenCL-based FPGA-GPU hybrid-layer platform to efficiently accelerate ECG signal diagnosis. As a result of diagnosing 19870 number of ECG signals of MIT-BIH arrhythmia database on the platform, the FPGA accelerator takes 1.15s, that the execution time was reduced by 89.94% and the power consumption was reduced by 84.0% compared to the software execution. The GPU accelerator takes 1.87s, that the execution time was reduced by 83.56% and the power consumption was reduced by 62.3% compared to the software execution. Although the proposed FPGA-GPU hybrid platform has a slower diagnostic speed than the FPGA accelerator, it can operate a flexible algorithm according to the situation by using the GPU.

Electrocardiogram (ECG) 신호는 심장의 이상을 조기에 진단하기 위한 좋은 지표이다. ECG 신호는 사람마다 기준이 되는 정상 신호의 형태가 다르고, 진단에 많은 데이터가 필요하다. 본 논문에서는 ECG 신호 진단을 효율적으로 가속하기 위한 OpenCL을 기반 FPGA-GPU 혼합 계층 적응형 플랫폼을 제안한다. 플랫폼에서 MIT-BIH 부정맥 신호데이터의 19870개 ECG 신호를 진단한 결과 FPGA 가속기는 진단 시간이 1.15s로 소프트웨어로 실행했을 때보다 89.94% 감소하였고, 전력 소모는 84.0% 감소하였다. GPU 가속기는 실행 시간이 소프트웨어 대비 83.56% 감소한 1.87s였으며, 전력 소모는 62.3% 감소하였다. 제안하는 FPGA-GPU 혼합 플랫폼은 FPGA 가속기보다 진단 속도가 느리지만 GPU를 이용하여 상황에 따라 유연한 알고리즘을 동작할 수 있다.

Keywords

Acknowledgement

This study was supported by the BK21 FOUR project funded by the Ministry of Education, Korea (4199990113966, 10%), Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (NRF-2019R1A2C2005099, 10%), and Ministry of Education (NRF-2018R1A6A1A03025109, 10%, NRF-2020R1I1A1A01072343, 10%). This work was partly supported by Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No. 2021-0-00944, Metamorphic approach of unstructured validation/verification for analyzing binary code, 60%)

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