Acknowledgement
This work was partly supported by National Natural Science Foundation of China (No. 51877050) and Natural Science Foundation of Heilongjiang Province, China (No. E2016031) and Hebei Provincial Project for Training and Supporting Talent (No. A201901119).
References
- Santos Filho, R.M., Seixas, P.F., Cortizo, P.C., et al.: Comparison of three single-phase PLL algorithms for UPS applications. IEEE Trans. Ind. Electron. 8, 2923-2932 (2008) https://doi.org/10.1109/TIE.2008.924205
- Zhang, X., Xia, D., Fu, Z., Wang, G., Xu, D.: An improved feed-forward control method considering PLL dynamics to improve weak grid stability of grid-connected inverters. IEEE Trans. Ind. Appl. 5, 5143-5515 (2018) https://doi.org/10.1109/TIA.2018.2811718
- Choi, Y., Lee, H., Kang, B., Lee, S., Yoon, S.: Compact single-stage micro-inverter with advanced control schemes for photovoltaic systems. Energies 12, 1-15 (2019) https://doi.org/10.3390/en12010001
- Bierhoff, M.H.: A general PLL-type algorithm for speed sensorless control of electrical drives. IEEE Trans. Ind. Electron. 12, 9253-9260 (2017) https://doi.org/10.1109/TIE.2017.2711568
- Gu, C., Wang, X., Shi, X., Deng, Z.: A PLL-based novel commutation correction strategy for a high-speed brushless DC motor sensorless drive system. IEEE Trans. Ind. Electron. 5, 3752-3762 (2018)
- Zhou, S., Zou, X., Zhu, D., et al.: An improved design of current controller for LCL-type grid-connected converter to reduce negative effect of PLL in weak grid. IEEE J Emerg Sel Top Power Electron. 2, 648-663 (2018) https://doi.org/10.1109/JESTPE.2017.2780918
- Golestan, S., Monfared, M., Freijedo, F.D.: Design-oriented study of advanced synchronous reference frame phase-locked loops. IEEE Trans. Power Electron. 2, 765-778 (2013) https://doi.org/10.1109/TPEL.2012.2204276
- Silva, C.H., Pereira, R.R., Silva, L.E.B.: A digital PLL scheme for three-phase system using modified synchronous reference Frame. IEEE Trans. Ind. Electron. 11, 3814-3821 (2010)
- Nicastri and Nagliero, A.: Comparison and evaluation of the PLL techniques for the design of the grid-connected inverter systems. In Proceedings IEEE International Symposium on Industrial Electronics, 3865-3870 (2010)
- Xiao, F., Dong, L., Li, L., Liao, X.: A frequency-fixed SOGI-based PLL for single-phase grid-connected converters. IEEE Trans. Power Electron. 3, 1713-1719 (2017) https://doi.org/10.1109/TPEL.2016.2606623
- Karimi-Ghartemani, M., Karimi, H., Iravani, M.R.: A magnitude/phase-locked loop system based on estimation of frequency and in-phase/quadrature-phase amplitudes. IEEE Trans. Ind. Electron. 2, 511-517 (2004) https://doi.org/10.1109/TIE.2004.825282
- Golestan, S., Monfared, M.: Dynamics assessment of advanced single-phase PLL structures. IEEE Trans. Ind. Electron. 6, 2167-2177 (2013) https://doi.org/10.1109/TIE.2012.2193863
- Luo, L., Tian, H., Wu, F.: Effects of input harmonics, DC offset and step changes of the fundamental component on single-phase EPLL and elimination. J Power Electron. 4, 1085-1092 (2015) https://doi.org/10.6113/JPE.2015.15.4.1085
- Wu, F., Zhang, L., Duan, J.: A new two-phase stationary frame based enhanced PLL for three-phase grid synchronization. IEEE Trans. Circuits Syst. II, Exp. Briefs 3, 251-255 (2015)
- Chen, M., Peng, L., Wang, B., Kan, J.: PLL based on extended trigonometric function delayed signal cancellation under various adverse grid conditions. IET Power Electron. 10, 1689-1697 (2018) https://doi.org/10.1049/iet-pel.2017.0709
- Hamed, H.A., Abdou, A.F., Bayoumi, E.H.E.: EE EL-Kholy Frequency adaptive CDSC-PLL using axis drift control under adverse grid condition. IEEE Trans. Ind. Electron. 4, 2671-2682 (2017)
- Golestan, S., Guerrero, J.M., Vasquez, J.C.: A nonadaptive window-based PLL for single-phase applications. IEEE Trans. Power Electron. 1, 24-31 (2018) https://doi.org/10.1109/TPEL.2017.2713379
- Li, Y., Wang, D., Ning, Y., Hui, N.: DC-offset elimination method for grid synchronization. Electron. Pap. 5, 335-337 (2017)
- Hui, N., Wang, D., Li, Y.: A novel hybrid filter-based PLL to eliminate effect of input harmonics and DC offset. IEEE Access. 6, 19762-19773 (2018) https://doi.org/10.1109/access.2018.2821704
- Xie, M., Wen, H., Zhu, C., Yang, Y.: DC offset rejection improvement in single-phase SOGI-PLL algorithms: methods review and experimental evaluation. IEEE Access 5, 12810-12819 (2017) https://doi.org/10.1109/ACCESS.2017.2719721
- M. Karimi-Ghartemani, S. A. Khajehoddin, K. P. Jain, and A. Bakhshai.: Comparison of two methods for addressing DC component in phase-locked loop systems. In: Energy Conversion Congress and Exposition (ECCE), 2011 IEEE, Phoenix, AZ, 2011, 3053-3058
- Karimi-Ghartemani, M., Khajehoddin, S.A., Jain, P., Bakhshai, A., Mojiri, M.: Addressing dc component in PLL and notch filter algorithms. IEEE Trans. Power Electron. 1, 78-86 (2012)
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