한국표면공학회지 (Journal of the Korean institute of surface engineering)

  • 제53권3호
  • /
  • Pages.124-129
  • /
  • 2020
  • /
  • 1225-8024(pISSN)
  • /
  • 2288-8403(eISSN)
한국표면공학회 (The Korean Institute of Surface Engineering)
권호 표지
DOI QR코드

DOI QR Code

차세대 메모리 디바이스Gap-Fill 공정 위한 공간 분할 PE-ALD개발 및 공정 설계

Development of Space Divided PE-ALD System and Process Design for Gap-Fill Process in Advanced Memory Devices

  • 이백주 ((주)한화 / 기계 부분 연구소) ;
  • 황재순 ((주)한화 / 기계 부분 연구소) ;
  • 서동원 ((주)한화 / 기계 부분 연구소) ;
  • 최재욱 ((주)한화 / 기계 부분 연구소)
  • 투고 : 2020.05.08
  • 심사 : 2020.06.29
  • 발행 : 2020.06.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

This study is for the development of high temperature ALD SiO2 film process, optimized for gap-fill process in manufacturing memory products, using a space-divided PE-ALD system equipped with an independent control dual plasma system and orbital moving unit. Space divided PE-ALD System has high productivity, and various applications can be applied according to Top Lid Design. But space divided ALD system has a limitation to realize concentric deposition map due to process influence due to disk rotation. In order to solve this problem, we developed an orbit rotation moving unit in which disk and wafer. Also we used Independent dual plasma system to enhance thin film properties. Improve productivity and film density for gap-fill process by having deposition and surface treatment in one cycle. Optimize deposition process for gap-fill patterns with different depths by utilizing our independently controlled dual plasma system to insert N2and/or He plasma during surface treatment, Provide void-free gap-fill process for high aspect ratio gap-fill patterns (up to 50:1) with convex curvature by adjusting deposition and surface treatment recipe in a cycle.

키워드

참고문헌

  1. J.W. Lee, H.B. Kim, K.H. Choi, A Study on the Organic-Inorganic Multilayer Barrier Thin Films Using R2R Low-Temperature Atmospheric-Pressure Atomic Layer Deposition System, J. Korea Inst. Mat. Eng., 13 (2018) 51-58.
  2. D. Bo. Semple, Katie L. Nardi, N. Draeger, Dennis M. Hau., Area-Selective Atomic Layer Deposition Assisted by Self-Assembled Monolayers: A Comparison of Cu, Co, W, and Ru, Chem. Mat., 31, 5 (2019) 1635-1645. https://doi.org/10.1021/acs.chemmater.8b04926
  3. Rizwan Khan. B. Shone, Byeong, G. Ko, J.K. Lee, H.S. Lee, J.Y. Park, Area-Selective Atomic Layer Deposition Using Si Precursors as Inhibitors, Chem. Mat., 30, 21 (2018) 7603-7610. https://doi.org/10.1021/acs.chemmater.8b02774
  4. J.B. Ko, H.I. Yeom, S.H. Park, Plasma-Enhanced Atomic Layer Deposition Processed $SiO_2$ Gate Insulating Layer for High Mobility Top-Gate Structured Oxide Thin-Film Transistors, IEEE, 37 (2016) 39-42.
  5. Y.S. Lee, J.H. Han, J.S. Park, Joz. Park, Low temperature SiOx thin film deposited by plasma enhanced atomic layer deposition for thin film encapsulation applications, American. Vac. Soc., 35 (2017) 1116.
  6. R. Sawyer, H.W. Nesbitt, R.A. Secco, High resolution X-ray Photoelectron Spectroscopy (XPS) study of $K_2O-SiO_2$ glasses: Evidence for three types of O and at least two types of Si, J. Non-Cry. Sol, 358 (2012) 290-302. https://doi.org/10.1016/j.jnoncrysol.2011.09.027
  7. David S. Jensen, Supriya S. Kanyal, Nitesh Madaan, Silicon (100)/$SiO_2$ by XPS. Surface Sci. Spec. 20, 36 (2013) 26-31.
  8. D.T. Or, J. Collins, M. Chang, Directional $SiO_2$ etch using plasma pre-treatment and hightemperature etchant deposition, Appl. Mat. Inc., 14/466 (2016) 808-815.
  9. J.H. Kim, E.Y. Oh, B.C. Ahn, D.G. Kim, Performance improvement of amorphous silicon thin-film transistors with $SiO_2$ gate insulator by $N_2$ plasma treatment. Appl. Phys. Lett., 64 (1994) 775-780. https://doi.org/10.1063/1.111009
  10. T.K. Nam, H.H. Lee, T.J. Choi, S.G. Seo, C.M. Yoon, Low-temperature, high-growth-rate ALD of $SiO_2$ using aminodisilane precursor, Appl. Sur. Sci., 485, 15 (2019) 381-390. https://doi.org/10.1016/j.apsusc.2019.03.227
  11. F Koehler, D H Triyoso, I Hussain, S Mutas, H Bernhardt, Atomic Layer Deposition of SiN for spacer applications in high-end logic devices, Mat. Sci. and Eng., 41 (2012) 53-56.
  12. T. Tanimura, C. Hsiao, K. Akiyama, Y. Hirota, J. Sato, T. Kaitsuka, Effect of Plasma Process for $SiO_2$ Film on Sidewall, IEEE, 28, 3 (2015) 278-282.
  13. HY Yu, XC He, LQ Liu, JS Gu, XW Wei, Surface modification of polypropylene microporous membrane to improve its antifouling characteristics in an SMBR: $N_2$ plasma treatment, Water research, 41, 20 (2007) 4703-4709. https://doi.org/10.1016/j.watres.2007.06.039
  14. Yao JK, Chen SM, Sun XW, Kwok HS, He plasma treatment of transparent conductive ZnO thin films, Appl. Sur. Sci., 355 (2015) 702-705. https://doi.org/10.1016/j.apsusc.2015.07.165
  15. M. A. Lieberman, A. J. Lichtenberg, Principles of Discharges and Materials Processing, Wiley, New York, 1994, 307.
  16. W. Sinya, D.K. Domomi, Method of forming silicon nitride thin film, KR, 10-2019-0129024.
  17. Longjuan, Z. Yinfang, Y. Jinling, L. Yan, Z. Wei, X. Jing, L. Yunfei, Y, Fuhua, Dependence of wet etch rate on deposition, annealing conditions and etchants for PECVD silicon nitride film, J. Semiconductors, 30, 9 (2009) 217-301.
  18. Ro. Huszank, La. Csedreki, Zso. fia Kerte, Zso. fia., Determination of the density of silicon-nitride thin films by ion-beam analytical techniques (RBS, PIXE, STIM), J Radioanal Nucl Chem., 21 (2015) 118-123.
  19. T. Tatsumi, S. Fukuda, S. Kadomura, Etch Rate Acceleration of $SiO_2$ during Wet Treatment after Gate Etching. Jap. J. Appl. Phys, 32, 12 (1993) 335-339. https://doi.org/10.1143/JJAP.32.L335
  20. Tien-Chun Yang and Krishna C. Saraswat, Effect of Physical Stress on the Degradation of Thin $SiO_2$ Films Under Electrical Stress. IEEE, 47, 4 (2000) 428.