Bidirectional DC-DC Converter Based on Quasi-Sepic for Battery Charging System

Abstract

In order to satisfy the voltage levels of the low voltage battery side and high voltage DC bus, a high voltage gain with bidirectional operation is required. In this system, the cost effectiveness of the design is a critical factor; therefore, the system should be designed using a small number of components. This paper propose a novel bidirectional converter composed with a quasi-sepic and switched-indictor network. The proposed converter consists a small number of components with a high voltage gain ratio. Detailed analysis are made with respect to the operating mode, number of components, voltage and current ripple and efficiency. To verify performance of the proposed converter, simulation was performed is this paper. The simulation results are shown to verify the feasibility and performance of the proposed bidirectional converter.

1. Introduce

Energy sorage system(ESS) with DC-DC converters operating in bidirectional is indispensable in microgrids, electric vehicles (EVs), and transportation system based on renewable energy [1,2]. Bidirectional DC-DC converters are essential for the transfer and conversion of the electrical energy of the storage units, which operate the charge and discharge processes. In general, the realization of highly efficient converters with large conversion ratios and high power densities is a significant challenge in the power electronic fields.

According to the conventional bidirectional converters with transformer [3]-[5], this type of converter benefits from a simple structure and easy to operate. However, the leakage indictance loss due to the high-frequency transformer results in a low converter efficiency. In [6]-[8], DC-DC converters operating in bidirectional with high conversion ratio were proposed. Practically, there have more power switches in these converters which led to increasing the conduction losses and the cost efficiency, lead to decrease the efficiency.

To overcome these problems, converters based on the integration of the boost converter with the Cuk, SEPIC, and buck-boost converters were presented in [9-11]. Which attained a high voltage gain ratio and low stresses across the power switches. However, the converters operate only in unidirectional mode, furthermore, the voltage and current stresses on the switches were not analysis in detail. Therefore, a novel DC-DC converter with quasi-sepic and switched inductor network are proposed in this paper.

In order to analyze the proposed converter, detailed analysis are processed with respected to the operating mode, number of components, voltage and current ripple and efficiency. The voltage ripple of the proposed converter is relatively low, which increase design flexibility for the passive components. The simulation results are shown to verify the feasibility and performance of the proposed bidirectional converter.

2. Bidirectional DC-DC converter with wide voltage conversion ratio

Figure 1 shows the schematic diagram of the proposed converter. The proposed converter consist of four power switches Q₁-Q₄; capacitors C₀-C₃, in addition, there are three in ductors L₁, L₂ and L₃ in the converter. The proposed converter was analyzed based on the assumption that the converter operate in continuous conduction mode (CCM), and that all the components are analyzed in ideal condition.

Fig. 1 Proposed converter

2.1 Construction of the proposed converter.

The presented converter is presented in Figure 1. The steady-state analyses with respect to the switching states of the converter are shown as follows:

When the converter operates in the boost mode, the power flows from the battery side to the dc bus side. In this mode, the gate signal of Q₁ and Q₂ are complementary to Q₃ and Q₄. The main theoretical waveform of the proposed converter in CCM are presented in Figure 3, and the topological states are described in Figure 2.

Fig. 2 Topological states of the converter in boost mode (a) [t0-t1] (b) [t1-t2]

Fig. 3 Main waveforms of boost mode.

[t0-t1]: When the circuit operates in this case. Switches Q₁ and Q₂ are ON, and switches Q₃ and Q₄ are turned OFF, as described in Figure 2 (a), during this time, the L₁ and L₂ are charged by the input voltage V_in, L₃ and C₂ are charged through C₂, C₁ and C₂ are discharged through the load resistance. The equation can be derived:

\(\begin{align}\left\{\begin{array}{l}U_{L 1}=U_{\text {low }} \\ U_{L 2}=U_{\text {low }} \\ U_{L 3}=U_{C 2}-U_{C 3} \\ U_{C 1}+U_{C 2}=U_{\text {high }}\end{array}\right.\end{align}\)       (1)

\(\begin{align}\left\{\begin{array}{l}i_{L 3}=-i_{C 2} \\ i_{C 3}=i_{L 3} \\ i_{C 1}=-i_{\text {high }}\end{array}\right.\end{align}\)       (2)

where U_L1, U_L2, U_L3 represent the voltages on the inductance. U_C1, U_C2, and U_C3 are the voltage on the capacitors. U_high and U_low are shown as the voltage on the DC bus side and voltage side. I_high and I_low are shown as the current on the DC bus side and battery side. These symbols are applicable to all of the converter in this paper.

[t1-t2]: When the circuit operates in this case. Switches Q₁ and Q₂ are OFF, and switches Q₃ and Q₄ are turned ON, as described in Figure 2 (b), L₁ and L₂ are discharged through Q₃ and C₂, L₃ is discharged through Q₄, output voltage is boosting through C₁ and C₂. The formulas below were derived for this state.

\(\begin{align}\left\{\begin{array}{l}U_{L 2}+U_{L 1}=U_{\text {low }}-U_{C 2} \\ U_{L 3}=-U_{3}=-U_{1} \\ U_{C 1}+U_{C 2}=U_{\text {high }}\end{array}\right.\end{align}\)       (3)

\(\begin{align}\left\{\begin{array}{l}i_{L 1}+i_{C 3}-i_{L 2}=i_{C 2} \\ i_{C 3}+i_{L 2}-i_{C 1}=i_{h i g h}\end{array}\right.\end{align}\)       (4)

By employing the ampere-second balance law to the inductance on the basic of (1) and (3), the voltage conversion ratio can be calculated as

\(\begin{align}M=\frac{1+3 d_{\text {Boost }}}{1-d_{\text {Boost }}}\end{align}\)       (5)

By employing the ampere-second balance law to the capacitors on the basic of (2) and (4), the average value of the inductor currents can be derived as

\(\begin{align}\left\{\begin{array}{l}I_{L 1}=I_{L 2}=\frac{1+3 d_{\text {Boost }}}{1-d_{\text {Boost }}} I_{\text {high }} \\ I_{L 2}=I_{\text {high }}\end{array}\right.\end{align}\)       (6)

When the proposed converter is applied to the buck mode, this is reverse to the boost mode, in which the gate signal of Q₁ and Q₂ is complementary with Q₃ and Q₄.. The characteristic waveform of the presented converter in CCM are described in Figure 4, and the topological stages are depicted in Figure 5.

Fig. 4 Main waveforms of buck mode.

Fig. 5 Topological states of the converter in buck mode (a) [t0-t1] (b) [t1-t2]

[t0-t1]: When the circuit operates in this case. Switches Q₁ and Q₂ are ON, and switches Q₃ and Q₄ are turned OFF, as described in Figure 5 (a).L₁ and L₂ are charging by C₂, then L₃ is charged by C₁ and C₃. The equation can be derived:

\(\begin{align}\left\{\begin{array}{l}U_{L 1}=U_{L 2}=\left(U_{C 2}-U_{\text {low }}\right) / 2 \\ U_{L 3}=U_{C 3}=U_{C 1} \\ U_{C 1}+U_{C 2}=U_{\text {high }}\end{array}\right.\end{align}\)       (7)

\(\begin{align}\left\{\begin{array}{l}i_{C 1}=i_{L 1}+i_{L 2}+i_{C 3}-i_{L 3} \\ i_{\text {high }}=i_{L 3}-i_{C 2}\end{array}\right.\end{align}\)       (8)

[t1-t2]: In the inductance charging mode, switching state is opposed to previous operation. In this state, C₃ and L₃ are in series connection to charge C₂. Moreover, L₁ and L₂ also discharging to C₀ through Q₁ and Q₂ on the basis of Figure 5(b). The equation can be derived:

\(\begin{align}\left\{\begin{array}{l}U_{L 1}=U_{L 2}=-U_{\text {low }} \\ U_{L 3}=U_{C 3}-U_{C o} \\ U_{C 1}+U_{C 2}=U_{\text {high }}\end{array}\right.\end{align}\)       (9)

\(\begin{align}\left\{\begin{array}{l}i_{L 3}=i_{L 3} \\ i_{L 1}=i_{L 2}=i_{C 2} \\ i_{C 1}=i_{\text {high }}\end{array}\right.\end{align}\)       (10)

Taking into account the volt-second balance law on L₁ and L₂ according to (8) and (10), the buck conversion Mbuck of the proposed converter in CCM can be obtained as

\(\begin{align}M_{B u c k}=\frac{d_{B u c k}}{4-3 d_{B u c k}}\end{align}\)       (11)

Moreover, it is concluded that the capacitor voltage can be deduced as

\(\begin{align}\left\{\begin{array}{l}U_{C 1}=U_{C 3}=\frac{U_{\text {low }}}{4-3 d_{\text {Buck }}} \\ U_{C 2}=\frac{\left(1-d_{\text {Buck }}\right) U_{\text {low }}}{d_{\text {Buck }}}=\frac{\left(1-d_{\text {Buck }}\right) U_{\text {high }}}{4-3 d_{\text {Boost }}}\end{array}\right.\end{align}\)       (12)

Using the ampere-second balance law of capacitors with (9) and (11), the average inductor current I_L1 and I_L2 of inductances L₁ and L₂ can be obtained as

\(\begin{align}\left\{\begin{array}{l}I_{L 1}=I_{L 1}=I_{\text {low }} \\ I_{L 3}=\frac{d_{\text {Buck }}}{4-3 d_{\text {Buck }}} I_{\text {low }}\end{array}\right.\end{align}\)       (13)

2.2 Comparisons with conventional converter

In general, the losses of the inductor, capacitor, and switch cause the parasitic effects on the converter. In these components, the inductor parasitic resistance has the greatest influence on the converter voltage conversion ratio. Therefore, when considering the influence of the inductance parasitic resistance, the voltage gain ratio of the conventional converter and the proposed converters can be expressed as follows

\(\begin{align}\begin{array}{l}M_{\text {Boost }}=\frac{1}{1-D}\left(\frac{1}{1+\frac{r 1}{(1-D)^{2} R}}\right) \\ M_{\text {Buck-Boost }}=\frac{D}{1-D}\left(\frac{1}{1+\frac{r 1}{(1-D)^{2} R}}\right) \\ M_{P-\text { converter }}=\frac{1+3 D}{1-D}\left(\frac{1}{1+\frac{r 1}{(1-D)^{2} R}}\right)\end{array}\end{align}\)       (14)

which D is the duty cycle, and r_l represent as the inductor parasitic resistance, R is the load resistance.

These three equations are derived by applying the volt-second balance law to inductors, if R/_rl is set to 0.01, the voltage gain ratio can be obtained under different duty cycle.

The comparison between the voltage conversion ratio and duty cycles of the proposed converter are shown in Figure 6. It can be seen that when considering the influence of parasitic components, voltage gain ratio sharply decrease at large duty cycle. However, under the same duty cycle, the voltage gain ratio of the proposed converters is higher than conventional converters. Therefore, under large duty cycle, the proposed converter has a better setp-up voltage performance than the conventional converters.

Fig. 6 Voltage gain ratio comparison between proposed converters and conventional converters with parasitic resistance

2.3 Voltage and current stresses on the switches

Voltage stress across the power switches: in accordance with the above analysis, as shown in Figure 4 and Figure 6. In addition, by employing the Kirchhoff voltage law (KVL) to the switches, it can be derived as

\(\begin{align}\left\{\begin{array}{l}U_{Q 1-\text { Boost }}=U_{Q 2-\text { Boost }}=\frac{U_{\text {low }}}{1-d_{\text {Bost }}}=\frac{U_{\text {high }}}{1+3 d_{\text {Bost }}} \\ U_{Q 3-\text { Boost }}=U_{Q 4-\text { Boost }}=\frac{2 U_{\text {low }}}{1-d_{\text {Boost }}}=\frac{2 U_{\text {high }}}{1+3 d_{\text {Boost }}}\end{array}\right.\end{align}\)       (15)

\(\begin{align}\left\{\begin{array}{l}U_{Q 1-\text { Buck }}=U_{Q 2-\text { Buck }}=\frac{U_{\text {high }}}{4-3 d_{\text {Buck }}} \\ U_{Q 3-\text { Buck }}=U_{Q 4-\text { Buck }}=\frac{2 U_{\text {high }}}{4-3 d_{\text {Buck }}}\end{array}\right.\end{align}\)       (16)

By using above analysis and the Kirchoff voltage law (KVL) to the switches, the voltage stress on the switches can be obtained as

\(\begin{align}\left\{\begin{array}{l}I_{Q 1-\text { Boost }}=I_{Q 2-\text { Boost }}=\frac{I_{\text {high }}}{1-d_{\text {Boost }}} \\ U_{Q 3-\text { Boost }}=U_{Q 4-\text { Boost }}=\frac{1}{1-d_{\text {Boost }}} I_{h i g h}\end{array}\right.\end{align}\)       (17)

\(\begin{align}\left\{\begin{array}{l}I_{Q 1-\text { Buck }}=I_{Q 2-\text { Buck }}=\frac{I_{\text {low }}}{4-3 d_{\text {Buck }}} \\ I_{Q 3-\text { Buck }}=I_{Q 4-\text { Buck }}=\frac{I_{\text {low }}}{4-3 d_{\text {Boost }}}\end{array}\right.\end{align}\)       (18)

2.4 Selection of inductors and capacitors

According to the current ripple of the inductances, the value of inductance can be calculated.

\(\begin{align}\left\{\begin{array}{l}I_{L 1}=I_{L 1}=\frac{1+3 d_{\text {Boost }}}{1-d_{\text {Boost }}} I_{\text {high }} \\ I_{L 2}=I_{\text {high }}\end{array}\right.\end{align}\)       (19)

\(\begin{align}\left\{\begin{array}{l}L_{1}=L_{2}=\frac{(1-D) V_{\text {low }}^{2} D T}{r_{i} \%(1+3 D) P} \\ L_{3}=\frac{V_{\text {low }}^{2} D T}{r_{i} \% P}\end{array}\right.\end{align}\)       (20)

The capacitors are designed according to the capacitor voltage ripple.

\(\begin{align}\left\{\begin{array}{l}i_{L 3}=-i_{C 2}=i_{Q 2}=\frac{1}{1-d_{\text {Boost }}} i_{\text {high }} \\ i_{L 3}=i_{C 3}=i_{Q 2}=\frac{1}{1-d_{\text {Boost }}} i_{\text {high }} \\ i_{C 1}=-i_{\text {high }}\end{array}\right.\end{align}\)       (21)

According to the current relationship of the capacitance, it can be derived that

\(\begin{align}\left\{\begin{array}{l}C_{1} \frac{\Delta_{C 1}}{D T}=-\frac{P_{O}}{V_{O}} \\ C_{2} \frac{\Delta_{C 1}}{D T}=-\frac{P_{O}}{\left(1-d_{\text {Boost }}\right) V_{O}} \\ C_{3} \frac{\Delta_{C 1}}{D T}=-\frac{P_{O}}{\left(1-d_{\text {Boost }}\right) V_{O}}\end{array}\right.\end{align}\)       (22)

The value of capacitance can be attained that

\(\begin{align}\begin{array}{l}C_{1}=-\frac{P_{o} D T}{r_{v} \% V_{o}} \\ C_{2}=-\frac{P_{O} D T}{r_{v} \% V_{o}\left(1-d_{\text {Boost }}\right)} \\ C_{2}=-\frac{P_{O} D T}{r_{v} \% V_{o}\left(1-d_{\text {Boost }}\right)}\end{array}\end{align}\)       (23)

3. Simulation results

To verify the theoretical analysis of the proposed converter, a 200-W prototype was simulated in PSIM. The parameters of the test prototype are presented in Table1. A double loop proportional-integral (PI) control, (inner current control loop and outer voltage control loop) as shown in Figure 7.

Fig. 7. Bidirectional power flow control strategy of proposed converter

Table 1. Parameters of the proposed converter

PSIM simulation results in boost mode is shown in Figure 8, when the duty cycle is equal to 0.6, the input voltage is 50V, and the output voltage is equal to 400V, which is satisfy the theoretical analysis.

Fig. 8 Simulation results of the inductors and output voltage in Boost mode

The voltage stress waveforms of Q₁-Q₄ in boost mode are presented in Figure 9. The voltage stresses on Q₁-Q₂ were 85V, which indicates the voltage stresses on Q₁-Q₂ are satisfy the equation (15), and the voltage stresses on Q₃-Q₄ were 240V, which also satisfy the equation (15).

Fig. 9 Simulation results of the voltage across Q1-Q4 in boost mode

PSIM simulation results in boost mode is shown in Figure 9, when the duty cycle is equal to 0.6, the input voltage is 65V, and the output voltage is equal to 520V, which is satisfy the theoretical analysis.

The voltage stress waveforms of Q₁-Q₄ in buck mode are presented in Figure 10. The voltage stresses on Q₁-Q₂ were 85V, which indicates the voltage stresses on Q₁-Q₂ are satisfy the equation (15), and the voltage stresses on Q₃-Q₄ were 240V, which also satisfy the equation (15).

Fig. 10 Simulation results of the inductors and output voltage in Buck mode

Fig. 11 Simulation results of the voltage across Q1-Q4 in buck mode

Characteristic of the proposed converter is shown in Table2, the duty cycle represent the PWM signal operate in Boost mode.

Table 2. Characteristic of the proposed converter

4. Conclusion

In this study, a novel bidirectional DC-DC converter without transformer and with high voltage gain was developed. The set of converter benefit from a high voltage conversion ratio in the boost and buck modes. Detailed analysis were made with respect to the opearting mode, number of components, current and voltage stresses on the switches. Finally, the experiment results were presented to verify the feasibility of the proposed converter. The results confirm that the converter provide a good trade-off between the voltage gain ratio, voltage and current stresses, and the components count.