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A Clock System including Low-power Burst Clock-data Recovery Circuit for Sensor Utility Network

Sensor Utility Network를 위한 저전력 Burst 클록-데이터 복원 회로를 포함한 클록 시스템

  • Song, Changmin (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology) ;
  • Seo, Jae-Hoon (Autosilicon) ;
  • Jang, Young-Chan (Department of Electronic Engineering, Graduate School, Kumoh National Institute of Technology)
  • Received : 2019.09.05
  • Accepted : 2019.09.25
  • Published : 2019.09.30

Abstract

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.

본 논문에서는 센서 유틸리티 네트워크에서 센서 노드들 사이의 주파수 차이로 인한 데이터 손실을 제거하기 위한 클록 시스템이 제안된다. 각 센서 노드를 위한 제안된 클록 시스템은 버스트 클록-데이터 복원 회로, 32-위상 클록을 출력하는 디지털 위상 고정 루프, 그리고 프로그래밍 가능한 개방형 루프 분수 분할기를 사용하는 디지털 주파수 합성기로 구성된다. 첫번째 센서 노드에는 버스트 클록-데이터 복원 회로 대신 능동 인덕터를 사용하는 CMOS 발진기가 사용된다. 제안된 클록 시스템은 1.2 V 공급 전압을 이용하는 65nm CMOS 공정에서 설계된다. 센서 노드들 사이의 주파수 오류가 1%일 때, 제안하는 버스트 클록-데이터 복원 회로는 기준 클록으로 5Mbps 데이터 속도에 대해 64배 체배된 주파수를 가짐으로 4.95 ns의 시간지터를 가진다. 설계된 디지털 주파수 합성기의 주파수 변경은 100 kHz에서 320 MHz의 주파수 범위에서 출력 클록의 한 주기 내에 수행된다.

Keywords

References

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