New Generalized PWM Schemes for Multilevel Inverters Providing Zero Common-Mode Voltage and Low Current Distortion

Abstract

This paper presents two advanced hybrid pulse-width modulation (PWM) strategies for multilevel inverters (MLIs) that provide both common-mode voltage (CMV) elimination and current ripple reduction. The first PWM utilizes sequences that apply one switching state at the double ends of a half-carrier cycle. The second PWM combines the advantages of the former and an existing four-state PWM. Analyses of the harmonic characteristics of the two groups of switching sequences based on a general switching voltage model are carried out, and algorithms to optimize the current ripple are proposed. These methods are simple and can be implemented online for general n-level inverters. Using a three-level NPC inverter and a five-level CHB inverter, good performances in terms of the root mean square current ripple are obtained with the proposed PWM schemes as indicated through improved harmonic distortion factors when compared to existing schemes in almost the entire region of the modulation index. This also leads to a significant reduction in the current total harmonic distortion. Simulation and experimental results are provided to verify the effectiveness of the proposed PWM methods.

I. INTRODUCTION

In recent years, multilevel inverters (MLIs) have been increasingly used in industry, especially in high-power inverter-fed medium-voltage (MV) drive applications [1]. Fig. 1 presents two popular topologies of an inverter-fed induction motor using MLIs including a five-level (5L) NPC inverter [Fig. 1(a)] and a 5L CHB inverter [Fig. 1(b)]. MLIs with multiple output voltage levels offer advantages over conventional two-level (2L) inverters such as an increased power rating, generation of output voltages with improved harmonic distortion, and reduced CMV [1]. In addition, based on a high number of switching states, many PWM techniques (PWMs) involving efficiency improvements such as reduced CMV, reduced current distortion, and lower switching losses have been developed.

Fig. 1. Five-level inverter-fed induction motor. (a) Five-level NPC inverter. (b) Five-level CHB inverter.

Common-mode voltages (CMVs) are associated with excessive bearing currents, which can cause premature motor bearing failure and electromagnetic interference [2], [3]. To mitigate the ill effects of CMV, enhanced PWMs using MLIs have attracted a lot of attention from researchers. In general, reduced CMV PWMs are classified into two groups. One group is related to partially eliminated CMV PWMs [4]-[7], while the other group is related to ZCMV PWMs [8]-[15].

In the application of PWM inverter-fed drives, current ripple is closely related to undesirable torque pulsation and additional PWM loss. For decades, harmonic investigation has been a subject of intensive research. Methods for reduced current ripple mainly involve the division of zero vector time [18]-[20], discontinuous PWMs [16], [24], [25], the division of active vector time [27], [33], and hybrid PWMs [20], [23].

Despite a greatly improved CMV when compared to traditional PWMs, the load current distortion with ZCMV PWMs is increased due to the use of the non-nearest vector in the space vector diagram [12]. This effect becomes more obvious in applications where a low switching frequency is preferred, such as high-power medium-voltage drives.

Up to now, most of the works concerning the improvement of current distortion have been confined to PWMs without consideration of the CMV. Recently, reduced current ripple PWMs for MLIs under the ZCMV condition have been reported in [13]-[15]. In [13], the sequences of three switching states per half-carrier cycle are covered. Based on switching voltage modeling generalized for a three-state PWM scheme with reduced switching loss, namely RL3ZS-PWM [12], a three-state ZCMV PWM strategy for reduced current ripple, namely RR3ZS-PWM, is developed. This method results in an improved root mean square (RMS) current ripple when compared to the RL3ZS-PWM in the entire modulation region of an n-level inverter, under various phase displacements [13]. The authors of [14] introduced a reduced current ripple PWM scheme, namely RR4ZS1-PWM, which covers four-state sequences of identical first and third states (or second and fourth states). The authors of [15] focused their investigation on sequences with identical first and fourth states for a three-level inverter. They also proposed an optimal algorithm that achieves a considerably improved harmonic performance when compared to previous works.

Four-state sequences, which are characterized by the double application of one among three active ZCMV vectors in a half-carrier cycle, can be classified into two groups. Group I includes the modified sequences presented in [14], while group II contains those with identical first and the fourth states [10], [15]. So far, the current ripple characteristics in a general n-level related to the four-state sequences in group II have not been investigated.

In this paper, two enhanced online PWM schemes for reduced current ripple in MLIs are proposed. Firstly, this paper formulates four generalized PWM patterns. Based on these patterns, all of the available four-state switching sequences in MLIs from group I and group II are deduced. This paper also thoroughly investigates the current ripple characteristics pertaining to the two groups of sequences. Secondly, an optimal PWM for a reduced RMS current ripple based on the sequences in group II, namely RR4ZS2-PWM, is generalized for an n-level inverter. Finally, an online hybrid PWM scheme, hereafter referred to as HRR4ZS-PWM, that combines the optimal sequences of the two mentioned groups is proposed to further improve the RMS current ripple.

The harmonic performances with the generalized RR4ZS2-PWM, and the further developed hybrid scheme HRR4ZS-PWM are investigated, and compared with those of the RR3ZS-PWM [13] and RR4ZS1-PWM [14].

This paper has analytically verified that both the proposed RR4ZS2-PWM and HRR4ZS-PWM have considerably improved RMS current ripple. In particular, the HRR4ZS-PWM, which combines the advantages of the proposed RR4ZS2-PWM and the RR4ZS1-PWM in [14], has the best harmonic performance when compared to the PWMs presented in [12]-[15]. The algorithms are straightforward to implemente online for a general n-level inverter using a digital signal processor controller.

Simulation and experimental results obtained from a 5L CHB inverter-fed volt-per-hertz (V/f) controlled induction motor have been presented to confirm the effectiveness of the proposed PWMs in eliminating CMV and reducing current distortion.

II. GENERALIZED ZCMV PWM SEQUENCES FOR MULTILEVEL INVERTERS

A. Switching Voltage Modeling of ZCMV PWM Control for Multilevel Inverters

CMV can be expressed in terms of pole voltages (each of which is measured from one output terminal to the mid-point O of the DC-link voltage) as [4]-[7]:

\(V_{C M}=V_{N O}=\frac{\left(V_{A O}+V_{B O}+V_{C O}\right)}{3}\)       (1)

Assume that each DC-link voltage, defined as V_dc in Fig. 1, is an ideal DC voltage. For a three-phase n-level inverter, the modulation index can be defined as:

\(m=\frac{v_{1 m}}{\frac{n-1}{\sqrt{3}} V_{d c}}\)       (2)

where v_1m is the peak magnitude of the fundamental phase voltage, and (n-1)V_dc/\(\sqrt{3}\) is the maximum value of v_1m that the inverter can produce in the linear PWM control. Under the ZCMV condition, the maximum value of v_1m is (n-1)V_dc/2, which limits the maximum modulation index in (2) to 0.866.

It has been demonstrated in [12] that the analytical processes for the NPC MLIs and CHB MLIs can be unified by a simple voltage modeling related to the normalized switching voltage V_Xn(X = A, B, C). V_Xn is defined by (3), where s_1X, s_2X, s_3X, ..., s_n-1X, represent the states of the switches SW_1X, SW_2X, ..., SW_n-1X, which are designated in Fig. 1 for the A-phase, and s_1X is 1 if SW_1X is on; otherwise, its value is 0.

\(V_{X n}=\sum_{j=1}^{n-1} s_{j X}=\frac{V_{X O}}{V_{d c}}+\frac{n-1}{2}, X=A, B, C\)       (3)

For diode-clamped inverter topologies, the additional constraint of s_jX, j∈{1, ..., n-1} in (3) is expressed as:

\(s_{1 X} \leq s_{2 X} \leq \cdots \leq s_{(n-2) X} \leq s_{(n-1) X}, X=A, B, C\)       (4)

The voltage V_Xn can be decomposed into two components as in (5), where L_X represents the base component of V_Xn, and s_X is the active component of V_Xn, where the value is 0 or 1.

\(V_{X n}=L_{X}+s_{X}, X=A, B, C\)       (5)

The average value of V_Xn can be expressed as:

\(v_{X n}=L_{X}+\xi_{X},\left(0 \leq \xi_{X} \leq 1, \xi_{X}=1 \text { if } v_{X n}=n-1\right)\)       (6)

where ζ_X(A, B, C) is the average value of s_X in a carrier cycle.

The base voltage and active voltage components are deduced from v_Xn as follows:

\(L_{X}=\left\{\begin{array}{l} \operatorname{Int}\left(v_{X n}\right) \text { if } v_{X n}       (7)

\(\begin{aligned} 0 \leq L_{X} \leq n-2 ; X =A, B, C \\ \xi_{X}=v_{X n}-L_{X}, X=A, B, C \end{aligned}\)       (8)

where Int(v_Xn) is a function that returns the nearest lower integer value of v_Xn.

B. Four Generalized ZCMV PWM Patterns

The total base voltage F_L and total active voltage F_e are defined as:

\(\begin{array}{l} F_{L}=L_{A}+L_{B}+L_{C} \\ F_{e}=\xi_{A}+\xi_{B}+\xi_{C} \end{array}\)       (9)

The ZCMV constraint leads to the conditions of F_L (or F_e) and the active switching states (s_A, s_B and s_C) as illustrated in Fig. 3.

Fig. 2. Conditions of F_L and the active switching states due to the ZCMV PWM control.

Fig. 3. Two generalized PWM patterns for the sequences of group I (in one half-switching cycle). (a) Pattern I (F_L = 3(n-1)/2-1). (b) Pattern II (F_L = 3(n-1)/2-2).

Fig. 3 and Fig. 4 present four generalized PWM patterns that can be utilized to derive all of the four-state PWM sequences in MLIs. The two pairs of patterns presented in Fig. 3 and Fig. 4 cover the sequences from group I and group II, respectively. The method of generating optimal sequences is presented in [14] for the sequences of group I. Meanwhile, it has yet to be developed for group II.

Fig. 4. Two generalized PWM patterns for the sequences of group II (in one half-switching cycle). (a) Pattern I (F_L = 3(n-1)/2-1). (b) Pattern II (F_L = 3(n-1)/2-2).

Considering Fig. 4, the Y₁-phase is defined as the phase where the corresponding first half of the active sequence is 0→1→0→0 for pattern I (or 1→0→1→1 for pattern II). Similarly, the Y₂-phase and Y₃-phase correspond to the sequences 0→0→1→0 for pattern I (or 1→1→0→1 for pattern II) and 1→0→0→1 for pattern I (or 0→1→1→0 for pattern II). s_Y1, s_Y2 and s_Y3 denote the three phase active switching states corresponding to the Y₁, Y₂ and Y₃ phases. In the first half of pattern I, it is shown that (s_Y1, s_Y2, s_Y3) = (0, 0, 1) is applied during the first and third time intervals of the half-carrier cycle with the sequences in group I, while it is distributed at the two ends with the sequences in group II.

The average values of s_Y1, s_Y2 and s_Y3 in one carrier cycle are defined as ζ_Y1, ζ_Y2 and ζ_Y3. Different three-phase mappings result in different three-phase active switching sequences. The duty cycles based on the two generalized PWM patterns of group II can be calculated as follows:

III. PROPOSED PWM ALGORITHMS FOR REDUCED OUTPUT-CURRENT RIPPLE IN MULTILEVEL INVERTERS

A. Current Ripple Characteristics in MLIs under the Condition of Zero CMV

The approximate current ripple expression of an X-phase in the Nth carrier cycle is described as follows [16]:

\(\tilde{\imath}_{X}=\frac{1}{L} \int_{N T_{S}}^{(N+1) T_{S}}\left(V_{X N}-v_{X 1}^{*}\right) d t, X=A, B, C\)       (12)

where V_XN and \(v_{X1}^{*}\) are the phase voltages measured from an X-terminal (X = A, B, C) to the load neutral N and its average value over one carrier cycle, respectively.

\(\tilde{\imath}_{X}\) in (12) can also be expressed in terms of the X-phase harmonic flux λ_X as:

\(\tilde{\imath}_{X}=\frac{1}{L} \lambda_{X}, X=A, B, C\)       (13)

It has been demonstrated in [13] that the load current ripple analysis of an n-level inverter under the condition of ZCMV can be simplified to that of a 2L inverter. This is due to the X-phase harmonic flux derived in the following equation:

\(\lambda_{X}=\frac{V_{d c N}}{n-1} \int_{N T_{S}}^{(N+1) T_{S}}\left(s_{X}-\xi_{X}\right) d t, X=A, B, C\)       (14)

where V_dcN = (n-1)V_dc, known as a generalized voltage factor, has a value that is the same for MLIs with an equal maximum linear output voltage.

For example, considering the two generalized PWM patterns described in Fig. 4, six types of active switching voltage waveforms can be classified. Since these waveforms are double-sided, it is sufficient to analyze the harmonic fluxes in one half-carrier cycle. The harmonic flux trajectories in the first half-carrier cycle corresponding to the switching voltage waveforms in Fig. 4 are illustrated in Fig. 5.

Fig. 5. Harmonic flux trajectories in the first half-carrier cycle corresponding to the phases of the sequences in group II. (a) Y₁-sequence (pattern I). (b) Y₁-sequence (pattern II). (c) Y₂-sequence (pattern I). (d) Y₂ -sequence (pattern II). (e) Y₃-sequence (Pattern I). (f) Y₃-sequence (Pattern II).

B. Proposed Generalized Optimal Algorithm for Reduced RMS Current Ripple Based on the Sequences in Group II

A four-state ZCMV PWM with reduced RMS current ripple generalized for an n-level inverter using sequences from group I was presented in [14]. In this paper, a generalized optimal algorithm based on sequences from group II is firstly investigated. Then a hybrid PWM that combines the optimal sequences from groups I and II is further developed.

The mean-square value of the harmonic flux (over one carrier cycle) corresponding to the Y_i-sequence (i = 1, 2, 3) in Fig. 6 is determined as:

\(\chi_{Y i}=\frac{2}{T_{S}} \int_{t\left(Y_{i}\right) 0}^{t_{\left(Y_{i}\right) 0}+\frac{T_{S}}{2}} \lambda_{Y i}^{2} d t,(i=1,2,3)\)       (15)

Fig. 6. Characteristics of χ_λn corresponding to PWMs with A → X₃, B → X₃ and C → X₃, and the RR4ZS2-PWM at: (a) α = 0°. (b) α = 15°.

By using a mathematical development similar to those used in [13], [14], χ_Y1, χ_Y2, χ_Y3 are obtained as follows:

\(\chi_{Y 1}=k \xi_{Y 1}^{2}\left(\xi_{Y 1}^{2}+3 \xi_{Y 2}^{2}-2 \xi_{Y 1}+1\right) T_{S}^{2}\)       (16)

\(\chi_{Y 2}=k \xi_{Y 2}^{2}\left(\xi_{Y 2}^{2}+3 \xi_{Y 1}^{2}-2 \xi_{Y 2}+1\right) T_{S}^{2}\)       (17)

\(\chi_{Y 3}=k \xi_{Y 3}^{2}\left(1-\xi_{Y 3}\right)^{2} T_{S}^{2}\)       (18)

where \(k=V_{d c N}^{2} /\left(48(n-1)^{2}\right)\).

χ_Yin(i = 1,2,3) is defined as the normalized value of χ_Yi expressed as:

\(\chi_{Y i n}=\frac{\chi_{Y i}}{V_{d c N}^{2} T_{S}^{2}},(i=1,2,3)\)       (19)

Then the total normalized mean-squared harmonic flux of three phases (over one carrier cycle) is expressed as follows:

\(\chi_{\lambda n}=\chi_{Y 1 n}+\chi_{Y 2 n}+\chi_{Y 3 n}\)       (20)

In total, there are six possible three-phase mappings: (A→Y₁, B→Y₂, C→Y₃), (A→Y₁, B→Y₃, C→Y₂), (A→Y₂, B→Y₁, C→Y₃), (A→Y₂, B→Y₃, C→Y₁), (A→Y₃, B→Y₁, C→Y₂) and (A→Y₃, B→Y₂, C→Y₁). Since the sum of χ_Y1n and χ_Y2n is the same when altering the roles of the sequences Y₁ and Y₂, the values of χ_λn are limited to those corresponding to three ways of single-phase mapping : A→Y₃, B→Y₃ and C→Y₃.

To achieve the objective of reducing the RMS current ripple, a method for determining the optimal mapping corresponding to the lowest χ_λn of the sequences in group II is investigated.

\(\chi_{\lambda n\left(X \rightarrow Y_{3}\right)}\)(X = A, B, C) is defined as the value of χ_{λ​​​​​​​n} due to mapping X→Y3. At the instant of sampling, the mapping A→Y3 is selected when the condition expressed below is satisfied:

\(\begin{array}{c} \chi_{\lambda n\left(X \rightarrow Y_{3}\right)}=\min \left(\chi_{\lambda n\left(A \rightarrow Y_{3}\right)}, \chi_{\lambda n\left(B \rightarrow Y_{3}\right)}, \chi_{\lambda n\left(C \rightarrow Y_{3}\right)}\right), \\ X=A, B, C \end{array}\)       (21)

Taking (16)-(20) into account, solving (21) leads to the following condition:

\(\xi_{A}=\operatorname{Max}\left(\xi_{A}, \xi_{B}, \xi_{C}\right)\)       (22)

For pattern II, the calculating process regarding the harmonic flux trajectories illustrated in Fig. 5(b)-(f) leads to:

\(\xi_{A}=\operatorname{Min}\left(\xi_{A}, \xi_{B}, \xi_{C}\right)\)       (23)

Similarly, the conditions of using the mappings B→Y3 and C→Y3 are derived as:

\(\left\{\begin{array}{l} \xi_{B}=\operatorname{Max}\left(\xi_{A}, \xi_{B}, \xi_{C}\right) \text { for Pattern } I \\ \xi_{B}=\operatorname{Min}\left(\xi_{A}, \xi_{B}, \xi_{C}\right) \text { for Pattern II } \end{array}\right.\)       (24)

\(\left\{\begin{array}{l} \xi_{C}=\operatorname{Max}\left(\xi_{A}, \xi_{B}, \xi_{C}\right) \text { for Pattern } I \\ \xi_{C}=\operatorname{Min}\left(\xi_{A}, \xi_{B}, \xi_{C}\right) \text { for Pattern II } \end{array}\right.\)       (25)

The rules for the X₁ and ܺX₂ sequences selection are designed for the symmetrical distribution of output voltage waveforms. Suppose the mapping A→Y₃ is utilized. Then the mappings of the B and C phases are obtained from the conditions as:

\(\left\{\begin{array}{l} \xi_{B} \geq \xi_{C}: B \rightarrow Y_{1}, C \rightarrow Y_{2} \\ \xi_{B}<\xi_{C}: B \rightarrow Y_{2}, C \rightarrow Y_{1} \end{array}\right. \text { for Pattern }I\)       (26)

and:

\(\left\{\begin{array}{l} \xi_{B} \leq \xi_{C}: B \rightarrow Y_{1}, C \rightarrow Y_{2} \\ \xi_{B}>\xi_{C}: B \rightarrow Y_{2}, C \rightarrow Y_{1} \end{array}\right. \text { for Pattern }II\)       (27)

Fig. 6 shows the comparative characteristics of χ_{λ​​​​​​​n} due to four PWMs using the sequences from group II, including those with A→Y₃, B→Y₃ and C→Y₃, and the optimal RR4ZS2-PWM, at α = 0^o (Fig. 6(a)) and α = 15^o (Fig. 6(b)). As can be seen in Fig. 6(a), the curve corresponding to the RR4ZS2-PWM at α = 0^o is the lowest when compared to the others. The optimal curve is identical to one with the mapping A→Y₃ in the ranges of 0 ≤ m ≤ 0.29 and 0.58 ≤ m ≤ 0.866, which is identical to the slices corresponding to the mappings B→Y₃ and C→Y₃ in the remaining range. At m = 0.43, the worst value of χ_{λ​​​​​​​n} is 6.4x10^-4, which falls into the case of A→Y₃. In addition, by using the optimal mapping of B→Y₃(or C→Y₃), χ_{λ​​​​​​​n} can be reduced by up to 74.6%. Similarly, the comparison in Fig. 6(b) indicates the optimal curve of χ_{λ​​​​​​​n} with the RR4ZS2-PWM at α = 15^o. The optimal mappings of A→Y₃ at m = 0.24 and B→Y₃ at m = 0.866 result in χ_{λ​​​​​​​n} with 56.4% and 64.57% reductions when compared to the worst case.

C. Proposed Hybrid Optimal PWM for Reducing RMS Current Ripple

From (16)-(23), optimal surface of the total normalized mean-squared harmonic flux of three phases χ_{λ​​​​​​​n} based on the sequences from group II can be determined. ζ_max, ζ_mid and ζ_min are defined as the maximum, medium and minimum values of ζ_A, ζ_B and ζ_C. Then the optimal value of χ_{λ​​​​​​​n} for pattern I based on group II is derived as:

\(\begin{array}{l} \chi_{\lambda n_{-} O p t 2}=p\left(\xi_{\min }^{2}\left(\xi_{\min }^{2}+3 \xi_{\operatorname{mid}}^{2}-2 \xi_{\min }+1\right)+\right. \\ \xi_{\operatorname{mid}}^{2}\left(\xi_{\operatorname{mid}}^{2}+3 \xi_{\min }^{2}-2 \xi_{\operatorname{mid}}+1\right)+\xi_{\max }^{2}\left(1-\xi_{\max }\right)^{2} \end{array}\)       (28)

where p = 1/(48(n-1)²).

For group I of the sequences, a similar mathematical development as in (16)-(23) for group II results in the optimal χ_{λ​​​​​​​n} as follows:

\(\begin{aligned} \chi_{\lambda n_{o p t 1}} &=p\left(4 \xi_{\min }^{2}\left(1-\xi_{\min }\right)^{2}\right.\\ &+\xi_{\operatorname{mid}}^{2}\left(\xi_{\operatorname{mid}}^{2}+3 \xi_{\min }^{2}-2 \xi_{\operatorname{mid}}+1\right) \\ &\left.+\xi_{\max }^{2}\left(\xi_{\operatorname{mid}}^{2}+4 \xi_{\min }^{2}-\xi_{\min } \xi_{\operatorname{mid}}\right)\right) \end{aligned}\)       (29)

Since the proposed hybrid PWM HRR4ZS-PWM covers the groups I and II, its minimum χ_{λ​​​​​​​n} is the lowest between the two values in (28) and (29), which is expressed as:

\(\chi_{\lambda n_{-} H R R 4 Z S}=\min \left(\chi_{\lambda n_{O p t 1}}, \chi_{\lambda n_{O p t 2}}\right)\)       (30)

By solving (30), a simple condition for optimal sequences selection with the HRR4ZS-PWM is finally derived for pattern I as:

\(2 \xi_{\min }\left(1-\xi_{\min }\right) \geq \xi_{\max } \xi_{\operatorname{mid}}: R R 4 Z S 2\)       (31)

else: RR4ZS1

A similar mathematical development applied to pattern II leads to the following condition:

\(2 \xi_{\max }\left(1-\xi_{\max }\right) \geq\left(1-\xi_{\operatorname{mid}}\right)\left(1-\xi_{\min }\right): R R 4 Z S 2\)       (32)

else: RR4ZS1

Fig. 7 illustrates the regional divisions of the two medium triangles in Fig. 2 using the HRR4ZS-PWM. In each medium triangle, three regions in green, which are contiguous to its three sides, are applied with the RR4ZS1-PWM. Meanwhile, the middle region is applied with the RR4ZS2-PWM. The regional division can then be generalized for a 5L inverter as shown in Fig. 8.

Fig. 7. Regional divisions of two medium triangles with the proposed HRR4ZS-PWM.

Fig. 8. Regional division of a space-vector diagram of a five-level inverter with the proposed HRR4ZS-PWM.

A flow diagram of the proposed hybrid PWM is illustrated for an n-level inverter as shown in Fig. 9. The RR4ZS2-PWM algorithm has been presented in Section II.B of this paper. A detailed description of the RR4ZS1-PWM can be found in [14].

Fig. 9. Proposed flow diagram of a hybrid ZCMV PWM applied to MLIs for reducing current ripple.

Fig. 10(a)-(c) shows the evaluated characteristics of χ_{λ​​​​​​​n} due to the RR4ZS1-PWM, the RR4ZS2-PWM and the HRR4ZS-PWM in the range of −30^o ≤ α ≤ 30^o using a 5L inverter.

Fig. 10. Total normalized mean-squared harmonic flux characteristic in the range of−30° ≤ α ≤ 30° due to: (a) RR4ZS1-PWM. (b) Proposed RR4ZS2-PWM. (c) proposed HRR4ZS-PWM.

The χ_{λ​​​​​​​n} characteristics due to the three PWMs at α=0^o and α=15^o are shown in Fig. 11(a) and Fig. 11(b), respectively. It can be seen that the proposed RR4ZS2-PWM has a better performance in terms of χ_{λ​​​​​​​n} over the RR4ZS1- PWM in a wide modulation region. For example, at (α=0^o, m = 0.29) and (α=15^o, m = 0.54), the RR4ZS2-PWM yields 33.1% and 37.1% reductions of χ_{λ​​​​​​​n} over the RR4ZS1-PWM. In the regions of 0.39≤ m ≤ 0.48 at α=0^o, 0.39 ≤ m ≤ 0.48, 0.63 ≤ m ≤ 0.77 and 0.84 ≤ m ≤ 0.866 at α=15^o, the RR4ZS1-PWM has lower χ_{λ​​​​​​​n}. For example, at (α=0^o, m = 0.42) and (α=15^o, m = 0.86), the χ_{λ​​​​​​​n} values with the RR4ZS1-PWM are 6.05% and 11.3% lower when compared to those of the RR4ZS2-PWM.

Fig. 11. Characteristics of χ_λn corresponding to the RR4ZS1-PWM, the proposed RR4ZS2-PWM and the HRR4ZS-PWM at: (a) α=0°. (b) α=15°.

As indicated in Fig. 11, by further combining advantages of the sequences from groups I and II using the algorithm in Fig. 9, the HRR4ZS-PWM results in the optimal χ_{λ​​​​​​​n} among those due to the four-state RR4ZS1-PWM and the RR4ZS2- PWM in the entire modulation region.

IV. HARMONIC DISTORTION FACTOR

The RMS value of the total normalized mean-squared harmonic flux in one output phase (for example, A-phase) is determined as follows:

\(H D F_{A}=\sqrt{\frac{1}{\pi} \int_{0}^{\pi} F_{A}(\theta) d \theta}\)       (33)

where:

\(F_{A}=\left\{\begin{array}{l} \chi_{X 1 n} \text { if } A \rightarrow X_{1} \\ \chi_{X 2 n} \text { if } A \rightarrow X_{2}, \text { for group } I \\ \chi_{X 3 n} \text { if } A \rightarrow X_{3} \end{array}\right.\)       (34)

\(F_{A}=\left\{\begin{array}{l} \chi_{Y 1 n} \text { if } A \rightarrow Y_{1} \\ \chi_{Y 2 n} \text { if } A \rightarrow Y_{2}, \text { for group } II \\ \chi_{Y 3 n} \text { if } A \rightarrow Y_{3} \end{array}\right.\)       (35)

and θ=2πf_ot, f_o is the output fundamental frequency.

The HDF_A in (33) is utilized as a harmonic distortion factor to theoretically evaluate the A-phase RMS current ripple [13], [14]. Since there is a total of eight commutations per carrier cycle with the three-state ZCMV PWM and twelve commutations with four-state ZCMV PWM, utilizing the same carrier frequency results in a 1.5 times increase in the average switching frequency (over one fundamental period) with the latter over the former. In order to equalize the average switching frequencies, the carrier frequency of the three-state PWM must be 1.5 times that of the four-state PWM. This leads to HDF_A values corresponding to the four-state PWMs being multiplied by a factor 1.5 [13], [14].

The HDF_A function is evaluated with existing reduced current ripple PWMs including the RR3ZS-PWM, RR4ZS1-PWM, and the proposed RR4ZS2-PWM and HRR4ZS-PWM. Comparative characteristics of the HDF_A are shown in Fig. 12(a) for a 3L inverter and in Fig. 12(b) for a 5L inverter.

Fig. 12. Harmonic distortion factor characteristics with the RR3ZSPWM, RR4ZS1-PWM, RR4ZS2-PWM and HRR4ZS-PWM of a: (a) Three-level inverter. (b) Five-level inverter.

As indicated in Fig. 12(a), the RR4ZS2-PWM has superior harmonic performance over both the RR3ZSPWM and the RR4ZS1-PWM in a wide modulation region of a 3L inverter. For example, at m = 0.6, reductions in the HDF_A with the RR4ZS2-PWM over the RR3ZS-PWM and RR4ZS1-PWM are 5.3% and 11.6%, respectively. When applying the proposed extended RR4ZS2-PWM algorithm for a 5L inverter, a significant harmonic improvement is obtained as illustrated in Fig. 12(b). For example, at m = 0.7, the RR4ZS2-PWM reduces the HDFA by 9.3% and 6.2% over the RR3ZS-PWM and RR4ZS1-PWM, respectively.

One can see that there are regions of HDF_A improvement with the RR4ZS1-PWM over the RR4ZS2-PWM. For example, the high modulation region of m ≥ 0.82 of a 3L inverter, and the middle region of 0.41≤ m ≤ 0.48 of a 5L inverter. It is indicated in Fig. 12 that the HRR4ZS-PWM further improves the harmonic performance of MLIs by using the advantages of the optimal sequences of both the RR4ZS1- PWM and the RR4ZS2-PWM. When compared to all of the presented PWMs, the HRR4ZS-PWM results in the lowest value of HDF_A in the all of the modulation regions of the two inverter topologies. The regions of significant improvements using the HR4ZS-PWM over the RR4ZS2-PWM are magnified in both figures. For the 3L inverter, the HRR4ZS-PWM has 2.1% and 3.1% lower HDF_A values when compared to the RR4ZS2-PWM at m = 0.2 and m = 0.85, respectively. At m = 0.1, m = 0.46 and m = 0.866 of the 5L inverter, there are 2.2%, 4.2% and 2.2% reductions of the HDF_A, respectively. Hence, it can be concluded that the HRR4ZS-PWM effectively combines the RR4ZS1-PWM in [14] with the proposed generalized RR4ZS2-PWM to further reduce the harmonic distortions in MLIs.

V. DEAD-TIME EFFECT ANALYSIS

As analyzed in Section II, the CMV using the proposed PWMs is always zero, considering the use of ideal switching components. In a real design, where the rising time and falling time of the switching devices are taken into account, a dead-time interval should be inserted between the switching signals corresponding to complementary SWs (for example, \(g_{S W_{2 A}}\) and \(g_{{\overline{S W}}_{2 A}}\)) to avoid short circuits. Depending on the current direction of the switching phase, the switching can be simultaneous or delayed by one dead-time interval. This leads to the appearance of CMV spikes when using the ZCMV PWM methods.

Assuming that i_A > 0, the conducting paths of phase A of a 5L NPC when V_A = 0 and V_A = V_dc are illustrated in Fig. 13(a) and Fig. 13(b), respectively. When considering the switching transition from V_A = 0 to V_A = V_dc, the switching state of (SW_1A, SW_2A, SW_3A, SW_4A) is changed from (0,0,1,1) to (0,1,1,1). The switching signal \(g_{S W_{2 A}}\) and its complementary \(g_{{\overline{S W}}_{2 A}}\) are flipped from 0 to 1 and from 1 to 0, respectively. The switching signals, when deadtime is added to the transition, are illustrated in Fig. 14.

Fig. 13. Conducting path of phase A of a 5L NPC inverter when i_A > 0 during: (a) V_A = 0. (b) V_A = V_dc.

Fig. 14. Switching signals and pole voltage V_A with transition of V_A when i_A > 0. (a) 0 → V_dc. (b) V_dc → 0.

From Fig. 13 and Fig. 14, it is obvious that i_A cannot flow through SW_2a until this switch is on. Thus, the positive current i_A delays the transition of the pole voltage V_A by an interval equal to the deadtime. A similar analysis is applied to the case where the transition is from V_A = V_dc to V_A = 0, as shown in Fig. 14(b). In this case, there is a simultaneous transition since the freewheeling diode, shown in Fig. 13(a), allows positive current to flow through.

Fig. 15 and Fig. 16 show a comparison of the Group I three-phase switching sequence (0, V_dc, -V_dc) → (0,2V_dc, −2V_dc) → (0, V_dc, -V_dc) → (V_dc,V_dc, −2V_dc) with and without considering the dead-time effect, when i_A > 0, i_B < 0, i_C > 0 . A CMV waveform is illustrated in each case. It can be seen that there is a spike, whose magnitude is -V_dc/3 , in the CMV waveform when adding deadtime. Similarly, the dead-time effect can be seen when investigating the Group II three-phase switching sequence (0, -V_dc, V_dc)→(V_dc, -V_dc, 0) →(0,0,0) → (0, -V_dc, V_dc), when i_A > 0, i_B < 0, i_C < 0 , as show in Fig. 16. In this case, the magnitude of the CMV is V_dc/3, as indicated in Fig. 16(b).

Fig. 15. Group I switching sequence and its CMV when i_A>0, i_B<0 and i_C>0. (a) Without considering the dead-time effect. (b) Considering the dead-time effect.

Fig. 16. Group II switching sequence and its CMV when i_A>0, i_B<0 and i_C<0. (a) Without considering the dead-time effect. (b) Considering the dead-time effect.

The dead-time effect can be solved by either shifting the dead-time in a software program [9] or by adding an extra circuit [11].

VI. SIMULATION AND EXPERIMENTAL RESULTS

A. Simulation Results

Using a 3L NPC inverter and a 5L CHB inverter, the performances of the proposed generalized RR4ZS2-PWM and the HRR4ZS-PWM when compared to those of the RR3ZS-PWM and the RR4ZS1-PWM are investigated through simulations. For gaining the maximum value of 380V RMS of the output line voltage in the linear range, the values of the DC-link voltage V_dc in the 3L inverter and the 5L inverter are set to 310 V and 155.5 V, respectively. For equal average switching frequencies, the carrier frequency of the RR3ZS-PWM is set to 2.7 kHz, and those corresponding to the four-state RR4ZS1-PWM, RR4ZS2-PWM and HRR4ZS-PWM are set to 1.8 kHz.

Comparison of the current THD values (THDs) with the four PWMs can be implied by that of the WTHD values (WTHDs) calculated from the obtained simulated waveform of the line voltage [20].

Fig. 17 (a) presents the WTHD characteristics of the RR3ZS-PWM, RR4ZS1-PWM, RR4ZS2-PWM and HRR4ZS-PWM versus the modulation index at an output frequency of 25 Hz for a 3L NPC inverter. Similar WTHD characteristics are shown in Fig. 17(b) for a 5L CHB inverter. For both topologies, it can be seen that there are improvements in terms of the WTHD with the RR4ZS2-PWM and the HRR4ZS-PWM in the modulation regions corresponding to their improved HDF_A, as presented in Fig. 12. The HRR4ZS-PWM has the best WTHD performance when compared to all of the other PWMs. For the 3L NPC inverter, the WTHD reductions with the HRR4ZS over the RR3ZS, RR4ZS1 and RR4ZS2 are 11.93%, 5.5% and 2.43% at m = 0.2. In addition, they are 19.56%, 1.6%, and 3.45% at m = 0.85. For the 5L inverter, these percentages are 11.93%, 5.54% and 2.43% at m = 0.1, and 13.2%, 2.76% and 2% at m = 0.866.

Fig. 17. Simulated WTHD characteristics with the RR3ZS-PWM, RR4ZS1-PWM, RR4ZS2-PWM and HRR4ZS-PWM at f_o = 25 Hz using a: (a) 3L NPC inverter. (b) 5L CHB inverter.

Fig. 18 presents simulated waveforms of a 5L cascaded inverter-fed V/f -controlled induction motor. The three-phase induction motor has the following parameters: stator resistance R_S= 8.68Ω, rotor resistance R_r= 8.3Ω, stator leakage inductance L_ls= 17.5mH, rotor leakage inductance L_lr=17.5mH, and magnetizing inductance L_m = 0.862H. The induction motor is operated with constant V/f control and the V/f ratio is fixed. As a result, the rated line voltage of 380V (RMS) corresponds to the rated frequency of 50 Hz.

Fig. 18. Simulation waveforms of a 5L inverter-fed V/f controlled induction motor, operating from 25 Hz to 50 Hz, using the proposed HRR4ZS-PWM method. (a) Rotor speed. (b) Stator currents. (c) Common-mode voltage.

The rotor speed, when the output frequency changes from 25Hz to 50Hz, is presented in Fig. 18(a). The three-phase stator current and CMV waveforms are shown in Fig. 18(b) and Fig. 18(c), respectively. It can be seen that zero CMV with the proposed HRR4ZS is obtained regardless of changes in the rotor speed.

CMV with the traditional sine-PWM (SPWM) under the same operating conditions as those in Fig. 18 is shown in Fig. 19. The CMV has a large magnitude and its peak value is roughly 311 V. A comparison between Fig. 18(c) and Fig. 19 indicates a significant improvement of the CMV with the proposed HRR4ZS PWM over the SPWM.

Fig. 19. Simulated waveform of the common-mode voltage of a 5L inverter-fed induction motor with V/f control, operating from 25 Hz to 50 Hz, using the traditional sine-PWM method (SPWM).

B. Experimental Results

The proposed PWMs are experimentally validated on a 5 KVA 5L CHB inverter-fed 2HP 380V-50Hz Y-connected induction motor. The experimental model is shown in Fig. 20.

Fig. 20. Experimental model of a 5L CHB inverter-fed induction Motor.

Each H-Bridge of the power circuit is made up of IGBTs (FGL-60N100-BNTD). The DC voltage on each H-Bridge is held constant at 155.5V. The rating of each DC-link capacitor used for the experimental setup is 10000µF. All of the PWM algorithms are implemented on a TMS320F28335 DSP microcontroller. The experimental carrier frequencies are 2.7kHz and 1.8kHz for the three-state and four-state PWMs, respectively.

The Y-connected induction motor has the same parameters and V/f ratio as the one used for the simulation verification in Section VI.A.

The CMV is measured from the load neutral N to the mid-point O of the DC-link voltage as indicated in Fig. 1(b).

Fig. 21(a) and Fig. 21(b) show experimental CMV waveforms and corresponding harmonic spectra with the proposed RR4ZS2-PWM and HRR4ZS-PWM at an output frequency of 50 Hz. From the FFT analysis, it can be seen that the proposed PWMs result in CMVs with a significant reduction in the magnitudes of the harmonic components when compared to the conventional SPWM, as investigated in [12]. It can be observed that the high frequency spikes with the highest magnitude of 50V appear in the experimental CMV waveforms. This is due to the dead-time effect, which has been theoretically studied in Section V.

Fig. 21. Experimental CMV waveforms and CMV harmonic spectra at f_o= 50 Hz using a five-level CHB inverter with the: (a) RR4ZS2-PWM. (b) HRR4ZS-PWM.

Fig. 22(a) and Fig. 22(b) present experimental stator currents with the proposed RR4ZS2 PWM and HRR4ZS PWM at f_o = 25 Hz (m = 0.433) and f_o = 50 Hz) m = 0.866), respectively. The instantaneous current ripple can be obtained by subtracting the fundamental current component from the stator current. As a post-processing step, a low-pass filter (LPF) is applied to remove the switching noise in the current ripples. Since the switching noise has a much higher frequency than the highest switching frequency of 2.7 ݇kHz,a cut-off frequency of 30 kHz is selected. The transfer function of the LPF is designed as follows:

\(H(s)=\frac{1}{1+s / 2 \pi f_{p}}\)       (36)

where f_p = 30 ݇kHz is the desired cutoff frequency.

Fig. 22. Experimental waveforms of stator current at f_o= 25 Hz with the: (a) Proposed RR4ZS2-PWM. (b) Proposed HRR4ZS-PWM (Y axis: 0.5A/div, X axis: 10ms/div).

 

Fig. 23. Experimental waveforms of stator current at f_o= 50 Hz with the: (a) Proposed RR4ZS2-PWM. (b) Proposed HRR4ZS-PWM (Y axis: 0.5A/div, X axis: 5ms/div).

Fig. 24. Experimental waveforms of phase current ripple at f_o= 25 Hz with the: (a) RR3ZS-PWM. (b) RR4ZS1-PWM. (c) Proposed RR4ZS2-PWM. (d) Proposed HRR4ZS-PWM.

Fig. 25. Experimental waveforms of phase current ripple at f_o= 50 Hz with the: (a) RR3ZS-PWM. (b) RR4ZS1-PWM. (c) Proposed RR4ZS2-PWM. (d) Proposed HRR4ZS-PWM.

Current ripple waveforms using the RR3ZS-PWM, RR4ZS1-PWM, RR4ZS2-PWM and HRR4ZS-PWM at f_o = 25 Hz  and f_o = 50 Hz are presented in Fig. 9 and Fig. 10, respectively. The RMS current ripple value calculated over a fundamental period is also provided in each case.

It can be observed that both the proposed RR4ZS2-PWM and HRR4ZS-PWM result in good performances in terms of the current ripple. The RR4ZS2-PWM has a 3% higher RMS current ripple than the RR4ZS1-PWM at f_o = 25 Hz. At ݂f_o = 50 Hz, the RMS current ripple with the RR4ZS2-PWM is 3% lower. For the proposed HRR4ZS2-PWM, the best RMS current ripples are indicated in both cases. At f_o = 25 Hz, its RMS current ripple is 18.7%, 1.23% and 3.45% lower when compared to the RR3ZS-PWM, RR4ZS1-PWM and RR4ZS2-PWM, respectively. At ݂f_o = 50 Hz, the reductions are 9.1%, 5% and 2.1%, respectively.

Fig. 26 presents comparative experimental RMS current ripple characteristics due to the four PWMs versus the output frequency at a step frequency of 5 Hz. It can be observed that there is a close agreement between these characteristics and the HDF_A characteristics in Fig. 12.

Fig. 26. Experimental RMS current ripple characteristics with the RR3ZS-PWM, RR4ZS1-PWM, RR4ZS2-PWM and HRR4ZS-PWM using a 5L CHB inverter.

In addition to the improvements in the current ripple at frequencies of 25 Hz and 50 Hz as presented in Fig. 24 and Fig. 25, good performances with the RR4S2-PWM and HRR4ZS-PWM are indicated at other analyzed frequencies. At f_o=15Hz (m = 0.25), there are 5.43% and 5.72% reductions in terms of the RMS current ripple with the RR4ZS2-PWM over the RR3ZS-PWM and RR4ZS1-PWM, respectively. At ݂f_o = 40Hz (m =0.693), these percentages of reduction are 7.1% and 4.84%, respectively. As previously mentioned, despite the good harmonic performance of the RR4ZS2-PWM, an exception can be found at ݂f_o= 25Hz (m = 0.433), where its RMS current ripple is 3% higher than that of the RR4ZS1-PWM.

Using the later developed HRR4ZS-PWM, the lowest RMS current ripple is obtained at all frequencies. At f_o= 45Hz (m = 0.779), the reduction with the HRR4ZS-PWM over that of the RR4ZS2-PWM is 0.9%, which helps improve the RMS current ripple up to 3.26% and 5.9% when compared to the RR3ZSPWM and RR4ZS1-PWM, respectively

Fig. 27 presents experimental current THDs due to the four ZCMV PWMs versus the output frequency. The obtained results are in good agreement with the comparative characteristics of the RMS current ripple pertaining to the four ZCMV PWMs in Fig. 26. Significantly improved harmonic performances with the RR4ZS2-PWM and HRR4ZS-PWM are obtained in a wide frequency range. As expected, the HRR4ZS-PWM results in the lowest THDs at almost all of the analyzed frequencies. At f_o = 25 Hz, the measured THD value with the HRR4ZS-PWM is similar to that of the RR4ZS1-PWM, and is 18.48% and 2.43% higher than those with the RR3ZS-PWM and RR4ZS2-PWM, respectively. At f_o = 50 Hz, the improvements in the current THD with the HRR4ZS-PWM over the RR3ZS-PWM, RR4ZS1-PWM and RR4ZS2-PWM are 7.6%, 4.2% and 1.5%, respectively.

Fig. 27. Experimental current THD characteristics with the RR3ZS-PWM, RR4ZS1-PWM, RR4ZS2-PWM and HRR4ZS-PWM using the 5L CHB inverter.

VII. CONCLUSION

Two enhanced ZCMV PWMs for multilevel inverters to reduce the RMS current ripple are proposed in this paper. Four standardized PWM patterns are formulated, which helps fully explore the current ripple characteristics pertaining to all of the four-state ZCMV PWM sequences in multilevel inverters. Then two simple online algorithms are proposed to reduce the current ripple. The performances of the proposed schemes have been compared to those of two existing ZCMV PWMs with reduced current ripple. In an analytical analysis, improved characteristics of the harmonic distortion factor are achieved with the two proposed PWMs in the wide linear modulation regions of a three-level inverter and a five-level inverter. It has been shown that the proposed hybrid PWM, which utilizes all of the available four-state sequences from the three nearest ZCMV vectors, has the most improved harmonic performance. The reduced RMS current ripple and reduced current THD indicated by both the simulation and experimental results have verified the effectiveness of the proposed schemes.