Double Boost Power-Decoupling Topology Suitable for Low-Voltage Photovoltaic Residential Applications Using Sliding-Mode Impedance-Shaping Controller

Abstract

This paper proposes a practical sliding-mode controller design for shaping the impedances of cascaded boost-converter power decoupling circuits for reducing the second order harmonic ripple in photovoltaic (PV) current. The cascaded double-boost converter, when used as power decoupling circuit, has some advantages in terms of a high step-up voltage-ratio, a small number of switches and a better efficiency when compared to conventional topologies. From these features, it can be seen that this topology is suitable for residential (PV) rooftop systems. However, a robust controller design capable of rejecting double frequency inverter ripple from passing to the (PV) source is a challenge. The design constraints are related to the principle of the impedance-shaping technique to maximize the output impedance of the input-side boost converter, to block the double frequency PV current ripple component, and to prevent it from passing to the source without degrading the system dynamic responses. The design has a small recovery time in the presence of transients with a low overshoot or undershoot. Moreover, the proposed controller ensures that the ripple component swings freely within a voltage-gap between the (PV) and the DC-link voltages by the small capacitance of the auxiliary DC-link for electrolytic-capacitor elimination. The second boost controls the main DC-link voltage tightly within a satisfactory ripple range. The inverter controller performs maximum power point tracking (MPPT) for the input voltage source using ripple correlation control (RCC). The robustness of the proposed control was verified by varying system parameters under different load conditions. Finally, the proposed controller was verified by simulation and experimental results.

I. INTRODUCTION

Residential photovoltaic (PV) systems, especially rooftop systems, require a high-level of safety and reliability. As smart grids spread, a high demand has emerged for house rooftop PV systems that can supply house needs and sell the surplus to the utility grid. One of the main safety issues is the higher PV source voltage required to supply the inverter DC-link. In addition, some system-components reduce the reliability and lifetime of the conditioner. Replacing electrolytic capacitors with film capacitors using a power decoupling circuit is one of the main approaches to increase the reliability and lifetime of converters. Most conventional circuits tend to compromise the reliability, lifetime and safety of PV converters [1]-[4]. Many power decoupling methods proposed in the literature [6]-[16], are DC-side power decoupling circuits. DC-side power decoupling circuits can be divided into two main categories; parallel and cascaded topologies. Fig. 1(a) shows the conventional parallel powerdecoupling strategy, which has a DC/DC converter connected in shunt with the main power circuit [8]. Typically, the power decoupling circuit is a bi-directional buck/boost converter. The cascaded power decoupling topology is based on two cascaded DC/DC converters as shown in Fig. 1(b). The auxiliary DC-link voltage is regulated to force the double-frequency ripple to oscillate around the average voltage value. In addition, the second boost controls the main DC-link voltage to have as small a ripple as possible. All of the conventional cascaded topologies were implemented to provide a high step-up voltage-ratio and a power-decoupling with electrolytic capacitors. The proposed cascaded topology enhances the step-up ratio higher than those of the conventional parallel topologies with a smaller number of switches and improved safety, reliability and efficiency. The high step-up ratio makes the circuit suitable for the low-voltage PV-sourced power conditioning systems that provide safety for residential roof-top applications [5]-[8]. This assures a low input voltage reducing the number of modules per string, which increases safety leading to simple protection circuits. Finally, the cascaded boost topologies do not use a low reliability bidirectional power decoupling converter as shown Fig. 1(a).

Fig. 1. Architecture comparison between power-decoupling circuits (V_AUX oscillates between a high V_DC and a low V_PV). (a) Typical parallel-type power decoupling circuit. (b) Proposed cascaded power-decoupling circuit.

As previously mentioned, the main idea of the proposed topology is to make the output capacitor of the front-end boost converter (the auxiliary DC-link) acts as a container for the second harmonics component (SHC) (see Fig. 1(b)). Meanwhile, the second-boost converter should be an easy path to deliver the SHC towards the auxiliary DC-link at the input. The input-side (front-end) boost converter ensures a high resistance to the SHC, which means it collects most of the SHC on the auxiliary DC-link. Therefore, the controller design is quite challenging.

In more detail, the second-boost converter controller is a PI with a high bandwidth to minimize the output impedance of the second-boost converter at the SHC frequency, which means the main DC-link voltage is nearly ripple-free (see Fig. 2(b)). This enhances the following single-phase inverter performance and efficiency. The PI controller design procedure was proposed in [17].

Fig. 2. Proposed cascaded double-boost power-decoupling circuit. (a) Power circuit. (b) Controller diagram.

Ripple correlation control (RCC) and another PI controller are applied to the single-phase inverter to track the maximum power point (MPP) of the PV source which enhances the system’s energy efficiency (see Fig.2 (b)).

The input-side boost converser controller aims to block the SHC from passing to the PV source and keeps it swinging around a specified average value on the auxiliary DC-link. Therefore, the input-side boost converter control design is the main issue in the proposed circuit. Thus, this paper focuses on designing the input-side boost converser control only.

Some approaches were proposed in [18]-[26] to solve this design issue. One of the earlier approaches is the dual-loop approach in [18], where the outer loop is a voltage loop that has a crossover frequency far below the SCH frequency and the inner loop is a current loop that has a faster bandwidth. The narrow bandwidth of the voltage loop degrades the system dynamic response and can introduce instability to the system [19]. Some following papers have tried to overcome the drawbacks of the dual loop approach. In [19], a notch filter was inserted in the voltage loop, and enhanced the voltage loop bandwidth. However, it adds a large negative phase shift at frequencies lower than the filter cutoff frequency, which can shrink the phase margin of the system [20]. Some other literatures proposed approaches to shape the output impedance of the input-side boost converter [21]-[26]. According to Mason’s Gain Formula, the number of forward paths can be used to shape the impedance, such as the feed-forward of the DC-link output voltage, the load current, or both of them (see [21], [22]). Furthermore, [23] added a virtual series-impedance to increase the output impedance of the input-side boost converter. Then, [24] proposed a combination of virtual series and parallel impedances to increase the output impedance and to compensate the system performance. These approaches aimed to shape the output impedance of the input-side boost converter to force the double frequency current ripple to bypass through a bulky DC-link capacitor. However, these approaches did not take into consideration a number of critical issues. 1) The practical design procedures are quite complicated, especially for electrolytic capacitor-less ripple rejection. 2) The robustness of the systems against line, load and circuit-parameter variations, where these approaches proved the stability around equilibrium point only. 3) Some of the proposed approaches degrade the system dynamic performance. All of the previous mentioned approaches use a linear controller, which has some limitations in terms of robustness and stability.

Recently, nonlinear control has attracted the attention of the power electronics and control researches since it can avoid linear control drawbacks. Sliding mode control (SMC) is a widely used nonlinear control that has the ability to handle wide deviations in the system parameters and uncertainty of system models [27], [28]. Moreover, SMC is more suitable for variable structure systems such as power electronic converters [28]-[39].

The implementation of SMC can be classified to direct SMC and indirect SMC. The direct SMC can be implemented by a direct application of the sliding surface to hysteresis modulation as in [32] and [34]. The direct SMC is easy to implement since there are no calculations needed. However, it suffers from frequency variations that affect the filtering stage. In addition, it is not robust to large transients in the circuit. The indirect SMC can be implemented by driving the equivalent control signal and then applying it to PWM. The implementation is quite complex because the equivalent control method is a model-based method as in [28]-[31]. The equivalent control method has a fixed frequency, which means it has an easy filter design. In addition, it is robust to disturbances in the circuit.

In this paper, a practical design of a sliding mode controller is proposed to shape the output impedance of an input-side boost converter. The SMC design starts by forming the sliding surface, which represents the control objective. The sliding surface is chosen as a double integral sliding mode control to remove the steady state error. In addition, this surface helps increase the forward paths, which means a greater reduction of the current ripple. Then the equivalent control method is used to design the SMC. Finally, the surface’s stable-gain ranges are designed using Routh–Hurwitz stability criterion.

The proposed control aims to maximize the output impedance of the input-side boost converter to block the double frequency PV current ripple components and to prevent it from passing to the source without degrading the system dynamics response. The topology of the low PV voltage and the high DC-link provides a wide voltage swing range at the auxiliary capacitive link, where the controller regulates the double frequency ripple component to swing around a specific average value (V_AUX in Fig. 1(b)). The proposed SMC method ensures the robustness of the system against variations in the line, load and the circuit parameters. Moreover, the proposed method ensures a faster transient response with lower overshoot and undershoots. Detailed design steps of the proposed control are introduced and compared with some previous impedance shaping approaches.

A. Objectives

The main objectives of this work can be summarized in the following points: 1) A low-input-voltage safety enhancement for PV residential applications assuring simpler and cheaper protection circuits. 2) A power-decoupling circuit to replace electrolytic capacitor with small film capacitor; that guarantees higher reliability and longer system lifetime. 3) Power-conversion-efficient, simple and cost-effective structure. 4) Modular strategy. 5) a practical design of SMC that has an ability to remove the SHC without degradation of the system dynamics.

B. Proposed Idea and Contributions

As previously mentioned, Fig. 1(a) shows a conventional parallel power-decoupling strategy that needs a reactive-power regulating converter connected in shunt with the main power rail. In this case, the power decoupling circuit is a bi-directional buck/boost topology, and the main power rail is a high step-up topology. In some previous references, a cascaded double-boost DC-DC topology was proposed to satisfy the high step-up ratio requirement. In this paper, a new topology based on the double boost converters is introduced (Fig. 1(b)). The difference from the previous works is that the output of the source-side pre-regulation boost (V_AUX) is not DC. Instead, it is free to oscillate in the double-frequency of the AC output around a controlled average voltage due to the link’s small capacitance. In addition, the second boost controls the main DC-link voltage within a demanded ripple range with small-capacitance film capacitors. Then, the extra power-decoupling converter can be removed.

The proposed cascaded topology has many contributions and advantages when compared to conventional parallel topologies. 1) The cascaded structure enhances the voltage step-up ratio. 2) The control configuration for the double boost does not need any reference signal from the PLL or AC power calculations from the inverter. 3) The number of switches is reduced, taking into account only one quadrant operation. 4) It has a more flexible design. The greater the voltage difference between the PV and the DC-link is, the smaller the link capacitance can be, which means an increase of the swing range of V_AUX is allowed. 5) The expected efficiency and the cost-effectiveness are improved since the number of switches and the power conversion stage are reduced. 6) The high step-up ratio makes the proposed circuit suitable for low-voltage high-safety PV applications.

In terms of control, replacing the conventional linear control with a nonlinear control that does not use a filtering stage enhances the system transient response and increases the control robustness.

The proposed controller uses the impedance shaping method, which has the ability to reshape double boost impedance to block the current ripple from passing to the source side without degradation of the system dynamics.

C. Challenges

The main challenge to implementing this topology is the control of the three cascaded converters, the double boosts and the single-phase inverter. The controller should be able to achieve a number of things. 1) The main DC-link should be as smooth as possible. 2) The double-frequency current-ripple from the AC inverter should bypass the main DC-link in the small capacitance as well as the second boost up to the auxiliary link. 3) The auxiliary link with its small capacitance should be left to oscillate with double the main frequency. 4) The pre-regulating boost should be able to keep the current ripple from bypassing to the PV source. 5) The PV-source voltage should be controlled to achieve MPPT operation. Fig. 2(b) shows an overall system block-diagram of the proposed power conditioning topology including the proposed controllers.

This paper is organized as follows. Section II provides a modelling of the cascaded double boost converter and the proposed SMC design. Section III provides a stability analysis of the SMC. Section IV provides the sliding-surface parameter design. Section V provides impedance-shaping and robustness analyses. Section VI provides a simulation verification. Section VII provides an experimental verification with a 0.5-kW module hardware prototype. Section VIII provides some concluding remarks.

II. PROPOSED SLIDING MODE CONTROLLER

In this section, a simplified model of a cascaded double boost converter is proposed. The detailed design of the proposed sliding mode control for input side boost converters is introduced.

A. Double Boost Converter Modeling

Assuming a robust inverter controller, the PV-voltage (V_PV) (see Fig. 2(a)) is regulated at a constant value. Thus, the input side boost converter can be simplified by an equivalent circuit as shown in Fig. 3. In this case, other assumptions are included. Thus, the input capacitor (C_s) dynamics can be neglected, the load side is assumed to be highly-resistive, and the equivalent series resistance (ESR) for both (L_B1) and (C_AUX) are neglected [24]. By applying Kirchhoff’s voltage and current laws to the circuit in Fig. 3, the following nonlinear differential equations can be obtained:

\(L_{B 1} \frac{d i_{L B 1}}{d t}=-\left(1-u_{1}\right) v_{A U X 1}+v_{s}\)       (1)

\(C_{A U X} \frac{d v_{A U X 1}}{d t}=\left(1-u_{1}\right) i_{L B 2}-\frac{v_{A U X 1}}{R_{B 2}}-i_{o}\)       (2)

where i_LB1 is the inductor current, u₁ is the control action, v_s is the input voltage, v_AUX1 is the auxiliary DC-link voltage, i_o is the load current disturbance, L_B1 is the input side boost converter inductor, C_AUX is the auxiliary DC-link capacitor, and R_B2 is the average load power of the first boost converter. The same procedures can be applied to the second boost converter by assuming that the average of the auxiliary DC-link voltage (V_AUX) is accurately regulated. The same previous model can be used for the second boost converter. The previous simplification helps in replacing the fourthorder double boost converter with two individual secondorder converters. Therefore, the control deign becomes less complicated.

Fig. 3. Equivalent circuit diagram of the first boost converter.

B. SMC Design

1) The Proposed Sliding Surface: To design the proposed sliding mode controller, the sliding surface should be selected according to the control objectives. In this paper, the sliding surface is chosen as a function of the error in the inductor current and the error in the auxiliary voltage, where the error in the auxiliary voltage is indirectly defined by the reference current of the inductor current as follows:

\(\psi_{1}=\alpha_{1} x_{1}+\alpha_{2} x_{2}\)       (3)

where:

\(x_{1}=i_{r}-i_{L B 1}\)       (4)

\(x_{2}=\int x_{1} d t\)       (5)

\(i_{r}=k_{1}\left(v_{r}-v_{A U X 1}\right)+k_{2} \int\left(v_{r}-v_{A U X 1}\right) d t.\)       (6)

where v_r is the desired auxiliary DC-link voltage, and ψ₁ is the switching function. α₁, α₂, ݇k₁ and ݇k₂ are the design parameters.

The proposed sliding surface has some advantages without any complication. The control signal has an integrator for the voltage error which helps remove the steady-state error of the voltage. The inductor current appears in the control signal, which improves the control dynamics. In addition, the output impedance of input-side boost increases due to an increase in the number of forward paths [23].

To make sure that the sliding surface is an attractor to the state trajectory, the following existence conditions should be valid at least in the neighborhood of the sliding manifold to fulfill the local reachability condition \(\lim _{\psi_{1} \rightarrow 0} \psi_{1} \dot{\psi}_{1}\) [27], [28]. By using (3) and its time derivative, the existence conditions are as follows:

\(\begin{aligned} \alpha_{1}\left(\frac{-k_{1}}{C_{A U X}} i_{C_{{A U X}_{min}} }\right.&+k_{2}\left(V_{r}-v_{A U X 1_{S S}}\right)-\frac{1}{L_{B 1}} V_{S \min } \\ &\left.+\frac{1}{L_{B 1}} v_{A U X 1_{S S}}\right)+\alpha_{2} x_{1 min }>0 \end{aligned}\)       (7)

\(\begin{aligned} \alpha_{1}\left(\frac{-k_{1}}{C_{A U X}} i_{C_{{A U X}_{max}} }\right.&\left.+k_{2}\left(V_{r}-V_{A U X 1_{S S}}\right)-\frac{1}{L_{B 1}} v_{S_{S S}}\right) \\ &+\alpha_{2} x_{1 max }<0 \end{aligned}\)       (8)

where (݅\(i_{C_{{A U X}_{min}}}\)) and (\(i_{C_{{A U X}_{max}}}\)) are the minimum and the maximum current of the auxiliary DC-link capacitor, (\(v_{{A U X 1}_{SS}}\)) is the steady state value of the DC-link voltage, (\(v_{{S}_{min}}\)) and (\(v_{{S}_{max}}\)) are the minimum and maximum input voltages, and (\(x_{{1}_{max}}\)) and (\(x_{{1}_{min}}\)) are the maximum and minimum inductor current errors.

\(\dot{\psi}_{1}=0\)       (9)

2) The Proposed Control Design: Once the state trajectory reaches the sliding surface, it should slide along the sliding surface towards the equilibrium point. The SM phase operation can be described by constant dynamics [27] as follows:

where (\(\dot{\psi}_{1}\)) is the time derivative of the switching function (ψ₁). Recalling (1)-(6) and using (9), the following equation are obtained:

\(\begin{array}{c} \alpha_{1}\left(\frac{-k_{1}}{c_{A U X}} i_{C_{A U X}}+k_{2}\left(v_{r}-v_{A U X 1}\right)-\frac{1}{L_{B 1}} v_{S}+\right. \\ \left.\frac{1}{L_{B 1}} v_{A U X 1}\left(1-u_{e q 1}\right)\right)+\alpha_{2} x_{1}=0. \end{array}\)       (10)

The control action that organizes the motion of the state trajectory along the sliding surface is called equivalent control signal [29]. By solving (10), the expiration for the equivalent control signal is as follows:

\(\begin{aligned} u_{e q 1}=1-\frac{1}{v_{A U X 1}}(& \frac{k_{1} L_{B 1}}{C_{A U X}} i_{C_{A U X}}-k_{2} L_{B 1}\left(v_{r}-v_{A U X 1}\right) \\ &\left.+v_{s}-L_{B 1} k_{3} x_{1}\right) \end{aligned}\)       (11)

where \(k_{3}=\frac{\alpha_{2}}{\alpha_{1}}\).

Then, rewrite (11) as follows:

\(\begin{array}{l} u_{e q 1}=\frac{1}{v_{A U X 1}}\left(v_{A U X 1}-v_{S}-\frac{k_{1} L_{B 1}}{C_{A U X}} i_{C_{A U X}}+\right. \\ \left(k_{2} L_{B 1}+k_{1} L_{B 1} k_{3}\right)\left(v_{r}-v_{A U X 1}\right)+ \\ \left.k_{2} L_{B 1} k_{3} \int\left(v_{r}-v_{A U X 1}\right) d t-L_{B 1} k_{3} i_{L B 1}\right) \end{array}\)       (12)

The following saturation condition should always be valid 0<u_eq1< 1 .

Fig. 4 shows a block diagram of the proposed input-side boost converter control (see equation (12)).

Fig. 4. Block diagram of the proposed input-side boost converter control (12).

III. SMC STABILITY ANALYSES

Using (2) to remove ݅\(i_{C_{A U X}}\), (12) can be rewritten as follows:

\(\begin{array}{l} \left(1-u_{e q 1}\right)=\frac{1}{\left(v_{A U X 1}-i_{L B 1} \frac{k_{2} L_{B 1}}{C_{A U X}}\right)}\left(v_{S}-\frac{k_{1} L_{B 1}}{C_{A U X} R_{B 2}} v_{A U X 1}-\right. \\ \frac{k_{1} L_{B 1}}{C_{A U X}} i_{o}-\left(k_{2} L_{B 1}+k_{1} L_{B 1} k_{3}\right)\left(v_{r}-v_{A U X 1}\right)- \\ \left.k_{2} L_{B 1} k_{3} \int\left(v_{r}-v_{A U X 1}\right) d t+L_{B 1} k_{3} i_{L B 1}\right) \end{array}\)       (13)

Substitute (13) into (1)-(2) and let \(\sigma_{1}=\int\left(v_{r}-v_{A U X 1}\right) d t\). The following ideal sliding mode dynamics of the converter represents the dynamics of the system on the sliding surface.

\(\begin{array}{l} \frac{d i_{L B 1}}{d t}=\frac{v_{s}}{L_{B 1}}-\frac{v_{A U X 1}}{L_{B 1}\left(v_{A U X 1}-i_{L B 1} \frac{k_{1} L_{B 1}}{C_{A U X}}\right)}\left(v_{S}-\right. \\ \frac{k_{1} L_{B 1}}{C_{A U X} R_{B 2}} v_{A U X 1}-\frac{k_{1} L_{B 1}}{C_{A U X}} i_{o}-\left(k_{2} L_{B 1}+k_{1} L_{B 1} k_{3}\right)\left(v_{r}-\right. \\ \left.\left.v_{A U X_{1}}\right)-k_{2} L_{B 1} k_{3} \sigma_{1}+L_{B 1} k_{3} i_{L B 1}\right) \end{array}\)       (14)

\(\begin{array}{l} \frac{d v_{A U X 1}}{d t}=\frac{i_{L B 1}}{C_{A U X}\left(v_{A U X 1}-i_{L B 1} \frac{k_{1} L_{B 1}}{C_{A U X}}\right)}\left(v_{S}-\frac{k_{1} L_{B 1}}{C_{A U X} R_{B 2}} v_{A U X 1}-\right. \\ \frac{k_{1} L_{B 1}}{C_{A U X}} i_{o}-\left(k_{2} L_{B 1}+k_{1} L_{B 1} k_{3}\right)\left(v_{r}-v_{A U X 1}\right)- \\ \left.k_{2} L_{B 1} k_{3} \sigma_{1}+L_{B 1} k_{3} i_{L B 1}\right)-\frac{1}{C_{A U X} R_{B 2}} v_{A U X 1}-\frac{1}{C_{A U X}} i_{o} \end{array}\)       (15)

The equilibrium point can be obtained by forcing the left terms of (14) and (15) to be equal to zero. Thus, the equilibrium point is as follows: V_AUX1 = V_r, \(I_{L B 1}=\frac{V_{r}^{2}}{R_{B 2} V_{S}}\), ݇k₂Σ = I_LB1, ܴ\(R_{B 2}=\frac{V_{r}^{2}}{P}\),  I_o= 0; where (V_AUX1), (I_LB1) and (Σ)are the steady state values of (V_AUX1), (i_LB1) and (σ₁), respectively. In addition, P is the load power.

To linearize (14)-(15) around the equilibrium point, every variable should be represented with its bias point small perturbation as follows:

\(\begin{array}{l} v_{s}=\hat{v}_{s}+V_{s}, v_{A U X 1}=\hat{v}_{A U X 1}+V_{A U X 1}, i_{L B 1}=\hat{\imath}_{L B 1}+I_{L B 1} \\ \sigma_{1}=\widehat{\sigma}_{1}+\Sigma_{1}, v_{r}=\hat{v}_{r}+V_{r}, i_{o}=\hat{\imath}_{o} \\ \text { where } V_{s} \gg \hat{v}_{s}, V_{A U X 1} \gg \hat{v}_{A U X 1}, I_{L B 1} \gg \hat{\imath}_{L B 1}, \Sigma_{1} \gg \widehat{\sigma}_{1}. \end{array}\)

After some mathematical derivation, using the equilibrium point and only considering the AC term, the linearized system is as follows:

\(\begin{aligned} \frac{d \hat{\imath}_{L B 1}}{d t}=a_{11} \hat{\imath}_{L B 1}+& a_{12} \hat{v}_{A U X 1}+a_{13} \widehat{\sigma_{1}}+b_{11} \hat{v}_{r}+b_{12} \hat{v}_{s} \\ &+b_{13} \hat{\imath}_{o} \end{aligned}\)       (16)

\(\begin{aligned} \frac{d \hat{v}_{A U X 1}}{d t}=a_{21} \hat{\imath}_{L B 1} &+a_{22} \hat{v}_{A U X 1}+a_{23} \widehat{\sigma_{1}}+b_{21} \hat{v}_{r} \\ &+b_{22} \hat{v}_{s}+b_{23} \hat{\imath}_{o} \end{aligned}\)       (17)

\(\begin{aligned} \frac{d \hat{\sigma}_{1}}{d t}=a_{31} \hat{\imath}_{L B 1}+&a_{32} \hat{v}_{A U X 1}+a_{33} \widehat{\sigma_{1}}+b_{31} \hat{v}_{r}+b_{32} \hat{v}_{s} & \\ &+b_{33} \hat{\imath}_{o} \end{aligned}\)       (18)

where the coefficients (a) and (b) are defined in the (A) matrix and (B) matrix (see eq. (19)).

The previous third-order linearized closed loop system can be reformed in this form \(\dot{\hat{x}} \equiv A \hat{x}+B \hat{u}\)

where \(\hat{x}=\left[\begin{array}{c} \hat{\imath}_{L B 1} \\ \hat{v}_{A U X 1} \\ \widehat{\sigma_{1}} \end{array}\right], \hat{u}=\left[\begin{array}{c} \hat{v}_{r} \\ \hat{v}_{s} \\ \hat{\imath}_{o} \end{array}\right]\),

\(\begin{array}{l} A=\left[\begin{array}{c} \frac{\mathrm{k}_{1} \frac{\mathrm{V}_{\mathrm{s}}^{2}}{\mathrm{V}_{\mathrm{r}}}+\mathrm{k}_{3} \mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}}{\mathrm{k}_{1} \mathrm{V}_{\mathrm{r}} \frac{\mathrm{L}_{\mathrm{B} 1}}{\mathrm{R}_{\mathrm{B} 2}}-\mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}} & \frac{-2 \mathrm{k}_{1} \frac{\mathrm{V}_{\mathrm{s}}}{\mathrm{R}_{\mathrm{B} 2}}+\mathrm{k}_{2} \mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}+\mathrm{k}_{1} \mathrm{k}_{3} \mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}}{\mathrm{k}_{1} \mathrm{V}_{\mathrm{r}} \frac{\mathrm{L}_{\mathrm{B} 1}}{\mathrm{R}_{\mathrm{B} 2}}-\mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}} & \frac{-\mathrm{k}_{2} \mathrm{k}_{3} \mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}}{\mathrm{k}_{1} \mathrm{V}_{\mathrm{r}} \frac{\mathrm{L}_{\mathrm{B} 1}}{\mathrm{R}_{\mathrm{B} 2}}-\mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}}\\ \frac{-\frac{V_{s}^{2}}{V_{r}}-\frac{V_{r}^{2}}{R_{B 2}} L_{B 1} k_{3}}{k_{1} V_{r} \frac{L_{B 1}}{R_{B 2}}-V_{s} C_{A U X}} & \frac{-\mathrm{k}_{1} \mathrm{L}_{\mathrm{B} 1} \mathrm{k}_{3} \frac{\mathrm{V}_{\mathrm{s}}}{\mathrm{V}_{\mathrm{r}}}-\mathrm{k}_{2} \mathrm{L}_{\mathrm{B} 1} \frac{\mathrm{V}_{\mathrm{s}}}{\mathrm{V}_{\mathrm{r}}}+\frac{2 \mathrm{V}_{\mathrm{s}}}{\mathrm{R}_{\mathrm{B} 2}}}{\mathrm{k}_{1} \mathrm{V}_{\mathrm{r}} \frac{\mathrm{L}_{\mathrm{B} 1}}{\mathrm{R}_{\mathrm{B} 2}}-\mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}} & \frac{\mathrm{k}_{2} \mathrm{L}_{\mathrm{B} 1} \mathrm{k}_{3} \frac{\mathrm{V}_{\mathrm{r}}}{\mathrm{R}_{\mathrm{B} 2}}}{\mathrm{k}_{1} \mathrm{V}_{\mathrm{r}} \frac{\mathrm{L}_{\mathrm{B} 1}}{\mathrm{R}_{\mathrm{B} 2}}-\mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}} \\ 0 & -1 & 0 \end{array}\right], \\ B=\left[\begin{array}{c} \frac{-\mathrm{k}_{2} \mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}-\mathrm{k}_{1} \mathrm{k}_{3} \mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}}{\mathrm{k}_{1} \mathrm{V}_{\mathrm{r}} \frac{\mathrm{L}_{\mathrm{B} 1}}{\mathrm{R}_{\mathrm{B} 2}}-\mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}} & \frac{\mathrm{k}_{1} \frac{\mathrm{V}_{\mathrm{r}}}{\mathrm{R}_{\mathrm{B} 2}}}{\mathrm{k}_{1} \mathrm{V}_{\mathrm{r}} \frac{\mathrm{L}_{\mathrm{B} 1}}{\mathrm{R}_{\mathrm{B} 2}}-\mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}} & \frac{-\mathrm{k}_{1} \mathrm{V}_{\mathrm{s}}}{\mathrm{k}_{1} \mathrm{V}_{\mathrm{r}} \frac{\mathrm{L}_{\mathrm{B} 1}}{\mathrm{R}_{\mathrm{B} 2}}-\mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}} \\ \frac{\mathrm{k}_{1} \mathrm{L}_{\mathrm{B} 1} \mathrm{k}_{3} \frac{\mathrm{V}_{\mathrm{r}}}{\mathrm{R}_{\mathrm{B} 2}}+\mathrm{k}_{2} \mathrm{L}_{\mathrm{B} 1} \frac{\mathrm{V}_{\mathrm{r}}}{\mathrm{R}_{\mathrm{B} 2}}}{\mathrm{k}_{1} \mathrm{V}_{\mathrm{r}} \frac{\mathrm{L}_{\mathrm{R} 1}}{\mathrm{R}_{\mathrm{B} 2}}-\mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}} & \frac{-V_{r}}{k_{1} V_{r} \frac{L_{B 1}}{R_{B 2}}-V_{s} C_{A U X}} & \frac{\mathrm{V}_{\mathrm{s}}}{\mathrm{k}_{1} \mathrm{V}_{\mathrm{r}} \frac{\mathrm{L}_{\mathrm{B} 1}}{\mathrm{R}_{\mathrm{B} 2}}-\mathrm{V}_{\mathrm{s}} \mathrm{C}_{\mathrm{AUX}}} \\ 1 & 0 & 0 \end{array}\right] \end{array}\)       (19)

The A matrix in (19) can be rewritten in a more general form as follows:

\(A=\left[\begin{array}{ccc} a_{11} & a_{12} & a_{13} \\ a_{21} & a_{22} & a_{23} \\ 0 & -1 & 0 \end{array}\right]\)

Then, apply this famous equation |sI - A| = |0 to get the characteristic equation of the system as follows:

\(\begin{array}{l} s^{3}-\left(a_{11}+a_{22}\right) s^{2}+\left(a_{11} a_{22}-a_{12} a_{21}+\right. \\ \left.a_{23}\right) s+\left(-a_{21} a_{13}-a_{23} a_{11}\right)=0 \end{array}\)       (20)

Therefore, according to the Routh-Hurwitz stability criterion, the conditions for stability are as follows:

\(q_{1}>0, q_{2}>\frac{q_{3}}{q_{1}}, q_{3}>0\)       (21)

where:

\(\begin{array}{l} q_{1}=-\left(a_{11}+a_{22}\right) \\ q_{2}=a_{11} a_{22}-a_{12} a_{21}+a_{23} \\ q_{3}=-a_{21} a_{13}-a_{23} a_{11}. \end{array}\)

These conditions define the stable range of the controllers.

IV. SLIDING SURFACE PARAMETER DESIGN

In this section, a design example of the control parameters and their effects on the system performance are illustrated. By using (21) and after some mathematical derivation, the stable ranges for the control parameters (݇k₁, k₂ and k₃) as a function in the circuit parameters are derived as follows:

\(\frac{2}{C_{A U X} R_{B 2}} k_{1}<k_{2}+k_{3} k_{1}<\frac{2 V_{S}}{V_{r} L_{B 1}}\)       (22)

\(0<k_{1}<\frac{C_{A U X} R_{B 2} V_{S}}{V_{r} L_{B 1}}.\)       (23)

By using Table I, the stable ranges of the parameters can be defined. In the following, the root locus are used to illustrate the effect of the control parameters on the roots of (20), which produces the effects on the stability and performance of the system. In Fig. 5, a very small range of the parameters is chosen for making the plot clearer.

TABLE I PARAMETERS VALUES OF THE HARDWARE PROTOTYPE

Fig. 5. Root locus of the closed loop. (a) k₂=1, k₃=2000 and 0.002< k₁<0.01. (b) k₁=0.002, k₃=2000 and 0.5< k₂<1.

In Fig. 5(a) (݇k₂=1) and (݇k₃=2000) are fixed, while ݇k₁ changes over the range of (0.002<k₁<0.01). The direction of the arrows points to the movement of the poles with an increasing ݇k₁. With an increasing (݇k₁), the system acts like an under-damped system. However, one of the poles is moving towards the right half plane. Therefore, ݇k₁ should be chosen carefully to give the desired performance and to keep the system stable. In Fig. 5(b) with an increasing ݇k₂ over the range of (0.5<k₂<1) while fixing (݇k₁=0.002 and ݇k₃=2000), the system acts like an over-damped system. ݇k₁ and ݇k₂ do not have any effect on the third pole, where the third pole is always real and its value is defined by ݇k₃. A trade-off of parameter values should be chosen to give the required performance and to keep the system stable.

The control parameter values can be obtained by comparing (20) with the following third-order characteristic equation [35]:

\(q(s)=(s+\alpha)\left(s^{2}+2 \omega_{n} \zeta s+\omega_{n}^{2}\right)\)       (24)

where (α) is a real value, (ω_n) is the natural frequency and (ߞ (is the damping ratio. These three variables can be chosen to achiever the needed performance and to keep the system poles in the left half plane. By solving the following three equations in three unknowns ( k₁, ݇k₂, ݇k₃ ), the control parameter values are obtained.

\(-a_{11}-a_{22}-2 \omega_{n} \zeta-\alpha=0\)       (25)

\(a_{11} a_{22}-a_{12} a_{21}-a_{23}-\omega_{n}^{2}-2 \alpha \omega_{n} \zeta=0\)       (26)

\(-a_{21} a_{13}+a_{23} a_{11}-\alpha \omega_{n}^{2}=0\)       (27)

The parameters should satisfy (7), (8), (22) and (23).

V. IMPEDANCE SHAPING AND ROBUSTNESS ANALYSES

A. Impedance Shaping Analyses

This section illustrates how the controller shapes the output impedance of the input-side boost converter to block the double frequency current ripple without degrading the system performance.

The output impedance can be driven by using this equation Z_out = C(sI-A)^-1B + D.After some mathematic derivations, the out impedance is as follows:

\(Z_{\text {Out}}=\frac{-V_{s}\left(f_{1}-f_{2} k_{1}\right) s}{\left(f_{1}-f_{2} k_{1}\right) s^{2}+\left(f_{3}+f_{4} k_{1}-f_{2} k_{2}\right) s+k_{2} f_{4}}\)       (28)

where (A) and (B) are in equation (19), \(C=\left[\begin{array}{lll} 0 & 0 & 0 \\ 0 & 0 & 0 \\ 0 & 1 & 0 \end{array}\right]\), D = 0, f₁ = C_AUXV_s, \(f_{2}=\frac{V_{r}}{R_{B 2}} L_{B 1}\), \(f_{3}=2 \frac{V_{s}}{R_{B 2}}\) and \(f_{4}=\frac{V_{s}^{2}}{V_{r}}\).

Fig. 6 shows the magnitude of (28) at 120Hz versus the control parameters. It can be seen that the output impedance of the input boost converter has its maximum value at (k₁ = 0), which cannot be used because the regulation of the auxiliary DC-link voltage depends on ݇k₁. Therefore, the (݇k₁) value is chosen to be near zero at 0.002. On the other hand, increasing (݇k₂) shifts the curve towards a lower impedance. Therefore, the (݇k₂) value is chosen as a trade-off to avoid degrading the system performance and to maximize the output impedance of the input-side boost converter.

Fig. 6. Output impedance of the input boost converter versus k₁ and k₂.

B. Control Robustness Verification

The robustness of the controller is checked against variations in the equilibrium point (Table I). Deviations in the load, the source, and the system parameters from the nominal conditions is studied through the root locus of the system poles in every case. It should be mentioned that the control parameters are the same for every case.

Fig. 7 shows the root locus for the poles. In Fig. 7(a), the arrows point to the movement of the poles with power increases (0.1 kW – 5 kW) at three different reference voltages. It can be noticed that the system under SMC regime is robust to a wide range of load variation with a small overshot at low power. In Fig. 7(b), the arrows point to the direction of the poles movement with the source voltage increased (50 V - 80 V) at three different constant loads. It can be noticed that the system is stable within a large variation in the source, which is quite suitable for renewable energy applications.

Fig. 7. Checking the robustness of the control through: (a) Changing the load power (0.1 kW-5 kW) at three different auxiliary DC-link voltages (200 V, 250 V and 350 V from left to right respectively); (b) Changing the input voltage (50 V-80 V) at three different load powers (0.1 kW, 0.5 kW and 5 kW from left to right respectively); (c) Changing the auxiliary DC-link capacitor value (10 μF-100 μF) at (0.1 kW and 0.5 kW).

On the other hand, the effects of input boost converter inductance variations on the system poles have been studied by changing the value over a wide range (0.3 mH-1.5 mH) at 0.5 kW. It is found that there is very small effect on the dominant poles of the system. In Fig. 7(c), the arrows point to the direction of the poles motions with auxiliary DC-link capacitor value (10 µF-100 µF) increases at two different input powers 0.1 kW and 0.5 kW. This does not have any effect on the dominant poles at 0.5 kW. Meanwhile the capacitance increase makes an overshot at 0.1 kW. However, the system is still stable. This result can be summaries as follows. The proposed sliding mode control can handle a wide variation and tolerance in the source, the load and the system parameters from the nominal values.

Moreover, Fig. 8 shows the phase trajectory for four different initial points in the (i_LB1,v_AUX) space. The trajectories successfully converge to the equilibrium point without depending on the initial point (P₁, P₂, P₃, P₄). It can be noticed that the system under the proposed SMC regime is an asymptotically stable system. Fig. 8 is drawn using the sampled data model of the boost converter (see eq. (29) and eq. (30)) and the sampled data model of the proposed control (see eq. (31)).

\(x\left(\left(k+d_{k}\right) T\right)=e^{A_{1} d_{k} T} x(k T)+A_{1}^{-1}\left(e^{A_{1} d_{k} T}-I\right) B_{1} v_{s}\)       (29)

\(x((k+1) T)=e^{A_{2}\left(1-d_{k}\right) T} x\left(\left(k+d_{k}\right) T\right)+A_{2}^{-1}\left(e^{A_{2}\left(1-d_{k}\right) T}-I\right) B_{2} v_{s}\)       (30)

\(d_{k}=\frac{v_{A U X 1_{k}}-v_{s_{k}-k_{1} L_{B 1} q_{k}+\left(k_{2} L_{B 1}+k_{1} L_{B 1} k_{3}\right) e_{k}+k_{2} L_{B 1} k_{3} y_{k}-L_{B 1} k_{3} i_{L B 1_{k}}}}{v_{A U X 1_{k}}}\)       (31)

and also equation (30) with \(x=\left[\begin{array}{c} i_{L B 1} \\ v_{A U X 1} \end{array}\right], A_{1}=\left[\begin{array}{cc} 0 & 0 \\ 0 & \frac{-1}{R_{B 2} C_{A U X 1}} \end{array}\right], B_{1}=\left[\begin{array}{c} \frac{1}{L_{B 1}} \\ 0 \end{array}\right]\), \(A_{2}=\left[\begin{array}{cc} 0 & \frac{-1}{L_{B 1}} \\ \frac{1}{C_{A U X_{1}}} & \frac{-1}{R_{B 2} C_{A U X 1}} \end{array}\right] \quad, \quad B_{2}=\left[\begin{array}{c} \frac{1}{L_{B 1}} \\ 0 \end{array}\right]\) and T is the sampling time. And also, eq. (31) has \(e_{k}=v_{r_{k}}-v_{A U X 1_{k}}, q_{k}=\frac{v_{A U X 1 k} -{v_{A U X 1_{k-1}}}}{T}, y_{k}=y_{k-1}+e_{k} T.\)

Fig. 8. Phase trajectory for different initial points (P₁, P₂, P₃, P₄).

VI. SIMULATION VERIFICATION

A dual loop PI control is designed to remove the PV current double frequency ripple (see Fig. 9), where the outer loop is a voltage loop that has been designed to have a crossover frequency far below the SCH frequency (PI voltage controller (PIC_V). Meanwhile, the inner loop is a current loop which has a faster bandwidth (PIC_I). G_B1i and G_B1vi are open loop transfer functions.

Fig. 9. PI control block diagram.

Then the circuit in Fig. 2(a) is built in the PSIM environment, with a digital implementation of the controller (see equation (12)). The circuit parameters are in Table I. Fig. 10 shows a comparison between the proposed SMC and a PI controller (see Fig. 9), where the two controllers have been applied to the same power stage in PSIM under the same conditions.

Fig. 10. Comparison between the proposed SMC and the two loops PI control under a 150-W step change in the input power. (a) PV voltage ripple. (b) PV current ripple. (c) Auxiliary DC-link voltage ripple.

Fig. 10(a) shows PV voltage waveforms for the two controllers individually. The voltage ripple with PI control is more than the double the voltage ripple under the SMC regime. On the other hand, Fig. 10(b) shows the PV current under both of the controllers. It can be noticed that the ripple under PI control is three times greater than the ripple under the SMC regime. Fig. 10(c) shows an auxiliary DC-link voltage waveform at a 30% step change of the input power. The recovery time of the SMC is 66 msec. Meanwhile, the PI takes 79 msec to reach the steady-state. Furthermore, the maximum voltage swings in the two previous periods are 269.78 V and 296.56 V, respectively. This illustrates that the SMC has a greater ability to reject ripple and a faster transient response with a lower overshoot than the PI controller.

VII. EXPERIMENTAL VERIFICATION

A prototype power circuit was built in the lab to validate the proposed scheme. All of the capacitors in the circuit are metalized-polypropylene film-type capacitors from Vishay with a capacitor of 25 µF and rated at 450-V DC. The PV input boost module has input and output capacitors of 25 µF. The inverter-side boost has only one 25-µF output capacitor. The module has 500 W of rated power. All of the switches used in the double boost converter circuit are silicon-carbide switches to improve efficiency. A dual Solar-Array simulator (ELGAR TerraSAS) was used as to simulate a PV array. The simulator contains 2-channels, where each channel is rated at a maximum of 15A and 80 V. The configurations were implemented on a TMS320F28335 with an XDS100v1 development board.

A. SMC Experimental Verification

The circuit is tested experimentally at 500 W with a constant input voltage reference as shown in Fig. 13.

In Fig. 11(a), it is shown that (from top to bottom) the PV voltage is regulated at 67 V with a 2.5-V peak-to-peak ripple, the auxiliary DC-link voltage is regulated at 250 V with a 200-V peak-to-peak ripple, and the main DC-link voltage is regulated at 400 V with a 12-V peak-to-peak ripple.

Fig. 11. The experimental results of 500-W test. (a) Three DC-link voltage waveforms. (b) PV and the second boost waveforms.

In Fig. 11(b), it is shown that (from bottom to top) the PV voltage is regulated under the same conditions, the PV current is regulated with a 1-A peak-to-peak ripple, the main DC-link voltage is regulated at 400 V with a 12-V peak-to-peak ripple and the second boost current. These results verify the operation of the circuit, where a 120 Hz AC component was successfully regulated at the auxiliary link. The peak-to-peak voltage is almost 200 V taking into account that the auxiliary capacitor values are smaller than 25 µF in practice. The input boost converter controller successfully blocks almost all of the ripple, preventing it from passing to the PV source.

The second boost converter controller successfully passes the AC component to the input boost converter, which can be seen from the second boost converter current waveform, the DC component plus the 120-Hz component.

B. MPPT Experimental Verification

The MPPT technique used is ripple correlation control (RCC) [36]. A block diagram of RCC is shown in Fig. 12. RCC is faster and easier to design.

Fig. 12. RCC MPPT block diagram.

RCC generates a maximum power point voltage reference that is used with an inverter PIC to force the system to work at the maximum power point.

The voltage step is calculated from the following equation:

\(\Delta V_{M P P}=\varphi \int f(t) d t\)       (32)

where \((t)=\frac{\Delta p}{\left(\Delta v_{P V}\right)^{2}}\). ∆p and ∆v_PV are changes in the PV power and the PV voltage, respectively. φ is a constant.

For testing the MPPT controller, under a fixed solar radiation (1000 W/m²) and temperature (25C°), the circuit is tested at 500 W. From the P-V curves of the employed PV source, the maximum power is 500 W at 64 V.

Fig. 13 shows the PV voltage, which is regulated at 64 V, the PV current, the main DC-link voltage and the auxiliary DC-link voltage (from bottom to top respectively), where the RCC tracks the MPP voltage successfully.

Fig. 13. MPPT experimental results.

The circuit was also tested under a cloudy day profile as shown in Fig. 14(a). Fig. 14(b) shows the obtained test results. The average MPPT efficiency produced is above 98%. This test illustrates that the proposed control has fast responses and it is robust to the rapid changes in the input power.

Fig. 14. Cloudy day test. (a) Solar radiation and temperature data profiles (cloudy day profile). (b) Cloudy-day profile results.

C. PI Control Experimental Verification

The PIC designed in section Ⅵ is experimentally tested at 0.5 kW. To improve the control performance, a notch filter was added to the voltage feedback in Fig. 9. The cut off frequency of the notch filter is 120 Hz.

In Fig. 15, it is shown that (from bottom to top) the PV voltage is regulated at 62 V with a 3-V peak-to-peak ripple, while the PV current ripple is around 5. In addition, the second boost current clearly shows that the second stage is working fine. By comparing these results with Fig. 11, it can be seen that the current ripple with the SMC is 1/5 the current ripple with the PI. Moreover, the SMC does not need a filtering stage design, which affects the system stability and the system transient response.

Fig. 15. PIC experimental results.

VIII. CONCLUSION

The paper proposed an electrolyte-less single-phase power conditioning system topology with a high step-up cascaded double boost converter suitable for PV residential applications. The reliability was enhanced through the use of small film capacitors instead of electrolyte capacitors. Furthermore, the output impedance shaping of the input-side boost converter for double frequency ripple component reduction in the PV current using sliding mode control has been proposed. The control successfully redacted the PV current double frequency ripple component without degrading the system dynamics response. The robustness and stability of the control have been varied. PSIM-simulations and 500-W experimental hardware tests have been used to verify the performance of the proposed topology. The proposed topology possesses the advantageous features of robustness and the elimination of electrolytic-capacitors for a high reliability and long lifespan when compared to conventional topologies.