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The Korean Institute of Electrical Engineers (대한전기학회)
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Improving Parallel Testing Efficiency of Memory Chips using NOC Interconnect

NOC 인터커넥트를 활용한 메모리 반도체 병렬 테스트 효율성 개선

  • Hong, Chaneui (School of Electronic and Display Engineering, Hoseo University) ;
  • Ahn, Jin-Ho (School of Electronic and Display Engineering, Hoseo University)
  • Received : 2018.08.27
  • Accepted : 2018.12.19
  • Published : 2019.02.01
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Abstract

Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.

Keywords

Acknowledgement

This research was supported by the MOTIE(Ministry of Trade, Industry & Energy(project number G3-37) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

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