Fig. 1. The block diagram of the MFxLMS algorithm.
Fig. 2. The block diagram of TMS320F280049 MCU.
Fig. 3. Analog front-end for anti-aliasing and amplification.
Fig. 4. Frequency response of the analog front-end.
Fig. 5. Adaptation of adaptive filter coefficients with delay memory move.
Fig. 6. Adaptation of adaptive filter coefficients without delay memory move.
Fig. 7. Level one of parallel processing using CLA.
Fig. 8. Level two of parallel processing using CLA.
Fig. 9. Comparison of the excution times between CPU and CLA with C code.
Fig. 10. Comparison of the excution times between CPU and CLA with assembly code.
Fig. 11. Hardware for the active noise controller using TMS320F280049 MCU module and analog front-end and back-end.
Fig. 12. System setup for multi-channel acitve noise controller.
Fig. 13. Comparison of the error signals with different convergence factors.
Fig. 14. Convergence behavior of the multi-sinusoidal noise.
Table1. The number of multiplications of the multi-channel MFxLMS algorithm.
Table 2. The maximum number of filter taps for real-time operation at each optimization stage.
참고문헌
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