DOI QR코드

DOI QR Code

1.9-GHz CMOS Power Amplifier using Adaptive Biasing Technique at AC Ground

  • Kang, Inseong (School of Electronic Engineering, Soongsil University) ;
  • Yoo, Jinho (School of Electronic Engineering, Soongsil University) ;
  • Park, Changkun (School of Electronic Engineering, Soongsil University)
  • Received : 2019.09.06
  • Accepted : 2019.11.13
  • Published : 2019.12.31

Abstract

A 1.9-GHz linear CMOS power amplifier is presented. An adaptive bias circuit (ABC) that utilizes an AC ground to detect the power level of the input signal is proposed to enhance the linearity and efficiency of the power amplifier. The ABC utilizes the second harmonic component as the input to mitigate the distortion of the fundamental signal. The input power level of the ABC was detected at the AC ground located at the VDD node of the power amplifier. The output of the ABC was fed into the inputs of the power stage. The input signal distortion was mitigated by detecting the input power level at the AC ground. The power amplifier was designed using a 180 nm RFCMOS process to evaluate the feasibility of the application of the proposed ABC in the power amplifier. The measured output power and power-added efficiency were improved by 1.7 dB and 2.9%, respectively.

Keywords

References

  1. S. Kang, D. Baek, and S. Hong, "A 5-GHz WLAN RF CMOS power amplifier with a parallel-cascoded configuration and an active feedback linearizer," IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 9, pp. 3230-3244, 2017. DOI: 10.1109/TMTT.2017.2691766.
  2. J. Yoo, C. Lee, I. Kang, M. Son, Y. Sim, and C. Park, "2.4-GHz CMOS linear power amplifier for IEEE 802.11n WLAN applications," Microwave and Optical Technology Letters, vol. 59, no. 3, pp. 546-550, 2017. DOI: 10.1002/mop.30343.
  3. Y. Jin and S. Hong, "A 2.4-GHz CMOS common-gate combining power amplifier with load impedance adaptor," IEEE Microwave and Wireless Components Letters, vol. 27, no. 9, pp. 836-838, 2017. DOI: 10.1109/LMWC.2017.2734748.
  4. Y. Hu and S. Boumaiza, "Doherty power amplifier distortion correction using an RF linearization amplifier," IEEE Transactions on Microwave Theory and Techniques, vol. 66, no. 5, pp. 2246-2257, 2018. DOI: 10.1109/LMWC.2017.2734748.
  5. A. K. Kwan, M. Younes, O. Hammi, M. Helaoui, and F.M. Ghannouchi, "Linearization of a highly nonlinear envelope tracking power amplifier targeting maximum efficiency," IEEE Microwave and Wireless Components Letters, vol. 27, no. 1, pp. 82-84, 2017. DOI: 10.1109/LMWC.2016.2629983.
  6. S. Chen, G. Wang, Z. Cheng, P. Qin, and Q. Xue, "Adaptively biased 60-GHz doherty power amplifier in 65-nm CMOS," IEEE Microwave and Wireless Components Letters, vol. 27, no. 3, pp. 296-298, 2017. DOI: 10.1109/LMWC.2017.2662011.
  7. J. Jang, J. Yoo, M. Lee, and C. Park, "A 2.4-GHz dual-mode CMOS power amplifier with a bypass structure using three-port transformer to improve efficiency," Journal of Korea Institute of Information and Communication Engineering, vol. 23, no. 6, pp. 719-725, 2019. DOI: 10.6109/jkiice.2019.23.6.719.
  8. S. Jang, C. Lee, and C. Park, "Differential 2.4-GHz CMOS power amplifier using an asymmetric differential inductor to improve linearity," Journal of Korea Institute of Information and Communication Engineering, vol. 23, no. 6, pp. 726-732, 2019. DOI: 10.6109/jkiice.2019.23.6.726.
  9. Y. Sim, J. Park, J. Yoo, C. Lee, and C. Park, "A CMOS power amplifier using an active balun as a driver stage to enhance its gain," Microelectronics Journal, vol. 63, pp. 160-169, 2017. DOI: 10.1016/j.mejo.2017.04.003.

Cited by

  1. 출력 전력 및 효율 개선을 위한 3-스택 구조의 Ku 대역 CMOS 전력 증폭기 vol.25, pp.1, 2019, https://doi.org/10.7471/ikeee.2021.25.1.133