Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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FPGA-based Implementation of Fast Histogram Equalization for Image Enhancement

영상 품질 개선을 위한 FPGA 기반 고속 히스토그램 평활화 회로 구현

  • Ryu, Sang-Moon (Department of Information and Control Engineering, Kunsan National University)
  • Received : 2019.08.01
  • Accepted : 2019.08.20
  • Published : 2019.11.30
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Abstract

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

영상 품질 개선을 위해 사용되는 히스토그램 평활화 알고리즘은 하드웨어 회로로 구현되면 소프트웨어로 구현된 경우보다 작업 속도 면에서 성능이 훨씬 뛰어나다. FPGA를 이용한 히스토그램 평활화 회로 구현에 대부분의 최신 FPGA에 포함된 곱셈기 회로와 상당량의 SRAM을 이용하고, 파이프라인을 적용하면 히스토그램 평활화 회로의 전체적인 동작 성능을 높일 수 있다. 본 논문은 이와 같은 방법을 적용하여 8비트 심도를 갖는 흑백 영상에 대해 히스토그램 평활화 작업을 고속으로 수행 가능한 FPGA 구현 방법을 제안한다. 제안된 회로는 FIFO를 이용하여 한 개의 영상에 대한 평활화가 진행되는 동안 다음 영상에 대한 히스토그램 계산을 수행할 수 있다. FIFO를 이용한 일부 작업의 시간적 중첩과 내장된 곱셈기 회로 그리고 파이프라인 적용 효과로 회로의 전체적인 성능은 대략 매 클럭마다 한 개의 화소에 대해 히스토그램 평활화를 수행할 수 있다. 그리고 영상을 분할하여 히스토그램 평활화 작업의 일부를 병렬 처리하면 그 성능을 속도 면에서 거의 두 배로 향상할 수 있다.

Keywords

References

  1. R. Kaur, and N. Kaur, "A review on image enhancement techniques," International Journal of Latest Trends in Engineering and Technology, vol. 4, no. 1, pp. 171-176, May. 2014.
  2. R. P. Singh, and M. Dixit, "Histogram equalization; a strong technique for image enhancement," International Journal of Signal Processing, Image Processing and Pattern Recognition, vol. 8, no. 8, pp. 345-352, Aug. 2015. https://doi.org/10.14257/ijsip.2015.8.8.35
  3. K. Santhi, and W. Banu, "Adaptive contrast enhancement using modified histogram equalization," International Journal for Light and Electron Optics, vol. 126, no. 19, pp. 1809-1814, Oct. 2015. https://doi.org/10.1016/j.ijleo.2015.05.023
  4. Sargun, and S. B. Rana, "A review of medical image enhancement techniques for image processing," International Journal of Current Engineering and Technology, vol. 5, no. 2, pp. 1282-1286, Apr. 2015. https://doi.org/10.14741/Ijcet/22774106/5.2.2015.121
  5. B. Oktavianto, and T. W. Purboyo, "A study of histogram equalization techniques for image enhancement," International Journal of Applied Engineering Research, vol. 13, no. 2, pp. 1165-1170, Feb. 2018.
  6. Z. Salcic, and J. Sivaswamy, "IMECO: A reconfigurable FPGA-based image enhancement co-processor framework," Real-Time Imaging, vol. 5, no. 6, pp. 385-395, Dec. 1999. https://doi.org/10.1006/rtim.1998.0134
  7. A.M. Alsuwailem, and S.A. Alshebeili, "A new approach for real-time histogram equalization using FPGA," in Proceeding of 2005 International Symposium on Intelligent Signal Processing and Communication Systems, Hongkong, pp. 397-400, 2005.
  8. C.-H. Lu, H.-Y. Hsu, and L. Wang, "A new contrast enhancement technique implemented on FPGA for real time image processing," in Proceeding of 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, Kyoto: Japan, pp. 542-545, 2009.
  9. J.-H. Kim, and H.-S. Park, "Efficient hardware architecture for histogram equalization algorithm for image enhancement," Journal of Korea Academy Industrial Cooperation Society, vol. 10, no. 5, pp. 967-971, May. 2009. https://doi.org/10.5762/KAIS.2009.10.5.967
  10. J.-H. Choi, J.-S. Park, and S. Lee, "A high-performance and low-cost histogram equalization scheme for full HD image," Journal of the Korea Inst. of Information&Communication Engineering, vol. 15, no. 5, pp. 1147-1154, May. 2011. https://doi.org/10.6109/jkiice.2011.15.5.1147
  11. S. Sim, S. Lee, H. Son, and K. Min, "Hardware design for improved histogram equalization," in Proceeding of 2012 Autumn Annual Conference of IEIE, Korea, pp. 218-222, 2012.
  12. K. S. Gautam, "Parallel histogram calculation for FPGA histogram calculation," in Proceeding of 2016 IEEE 6th International Conference on Advanced Computing, India, pp. 774-777, 2016.
  13. H.L. Sneha, "The why and how of pipelining in FPGAs," [Internet]. Available: https://www.allaboutcircuits.com/technical-articles/why-how-pipelining-in-fpga/.
  14. AXI4-stream protocol specification, ARM, 2010.
  15. Vivado Design Suite AXI reference guide, Xilinx, 2017.
  16. 7 Series FPGAs memory resources, Xilinx, 2019.
  17. 7 Series DSP48E1 slice user guide, Xilinx, 2018.