한국정보전자통신기술학회논문지 (The Journal of Korea Institute of Information, Electronics, and Communication Technology)

  • 제11권5호
  • /
  • Pages.475-480
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  • 2018
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  • 2005-081X(pISSN)
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  • 2288-9302(eISSN)
한국정보전자통신기술학회 (Korea Information Electronic Communication Technology)
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A Low-area and Low-power 512-point Pipelined FFT Design Using Radix-24-23 for OFDM Applications

  • Yu, Jian (Department of Electronic Engineering Wonkwang University) ;
  • Cho, Kyung-Ju (Department of Electronic Engineering Wonkwang University)
  • 투고 : 2018.10.11
  • 심사 : 2018.10.19
  • 발행 : 2018.10.30
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초록

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

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참고문헌

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