DOI QR코드

DOI QR Code

게이트 절연막과 게이트 전극물질의 변화에 따른 피드백 전계효과 트랜지스터의 히스테리시스 특성 확인

The hysteresis characteristic of Feedback field-effect transistors with fluctuation of gate oxide and metal gate

  • Lee, Kyungsoo (Dept. of Electrical Engineering, Korea University) ;
  • Woo, Sola (Dept. of Electrical Engineering, Korea University) ;
  • Cho, Jinsun (Dept. of Electrical Engineering, Korea University) ;
  • Kang, Hyungu (Dept. of Electrical Engineering, Korea University) ;
  • Kim, Sangsig (Dept. of Electrical Engineering, Korea University)
  • 발행 : 2018.06.30

초록

본 연구에서는 급격한 스위칭 특성을 달성하기 위해 싱글단일-게이트 실리콘 채널에서 전하 캐리어의 양의 피드백을 이용하는 새롭게 설계된 피드백 전계 효과 트랜지스터를 제안한다. 에너지 밴드 다이어그램, I-V 특성, 문턱전압 기울기 및 on/off 전류 비는 TCAD 시뮬레이터를 이용하여 분석한다. 피드백 전계 효과 트랜지스터의 중요한 특징 중 하나인 히스테리시스의 특성을 보기 위해 게이트 절연막 물질과 게이트 전극물질을 변경하여 시뮬레이션을 진행했다. 이러한 특성변화는 피드백 전계효과 트랜지스터의 문턱전압 ($V_{TH}$)을 변화시켰고, 메모리 윈도우 폭이 작아지는 현상을 보였다.

In this study, we propose newly designed feedback field-effect transistors that utilize the positive feedback of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I-V characterisitcs, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. To demonstrate the changing characteristics of hysteresis, one of the important features of the feedback field effect transistor, we simulated changing the gate insulating material and the gate metal electrode. The fluctuation in the characteristics changed the $V_{TH}$ of the hysteresis and showed a decrease in width of the hysteresis.

키워드

참고문헌

  1. Kim, Minsuk, et al. "Steep switching characteristics of single-gated feedback field-effect transistors." Nanotechnology, vol. 28, no. 5, pp. 055205-1-055205-8, 2017. DOI: 10.1088/1361-6528/28/5/055205
  2. Thompson, Scott E., and Srivatsan Parthasarathy. "Moore's law: the future of Si microelectronics." Materials today, vol. 9, no. 6 pp. 20-25, 2006. DOI:10.1016/S1369-7021(06)71539-5
  3. Jaesung Jo, Changhwan Shin. "Study of Temperature Effects on Negative Capacitance Field-Effect Transistor." IEEK (2014): 70-72.
  4. Sakurai Takayasu, "Perspectives of Low-Power VLSI'." IEICE Transactions on Electronics, vol. E87-C, no. 4, pp. 429-436, 2004.
  5. El Dirani, H., et al. "Competitive 1T-DRAM in 28 nm FDSOI technology for low-power embedded memory." SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016 IEEE. IEEE, 2016. DOI: 10.1109/S3S.2016.7804402
  6. Wan, Jing, et al. "A systematic study of the sharp-switching Z2-FET device: From mechanism to modeling and compact memory applications." Solid-State Electronics 90 (2013): 2-11. DOI:10.1016/j.sse.2013.02.060
  7. Jinsun Cho, et al. "Effect of Channel Length Variation on Memory Window Characteristics of single-gated feedback field-effect transistor." IKEEE 21.3 (2017): 284-287. DOI:10.7471/ikeee.2017.21.3.284
  8. Manual, ATLAS User'S. "Device simulation software." Silvaco Int. Santa Clara, CA, 2008
  9. Sze, Simon M., and Kwok K. Ng. Physics of semiconductor devices. John wiley & sons, 2006.

피인용 문헌

  1. Understanding of Feedback Field-Effect Transistor and Its Applications vol.10, pp.9, 2018, https://doi.org/10.3390/app10093070