참고문헌
- H. Kim, S. Lee, "A New Flash Memory Management for Flash Storage System," Proceedings of Computer Software and Applications Conference, pp. 284-289, 1999.
- H. Jo, J.U. Kang, S.Y. Park, J-S. Kim, J. Lee, "FAB: Flash Aware Buffer Management Policy for Portable Media Players," IEEE Transactions on Consumer Electronics, Vol. 52, No. 2, pp. 485-493, 2006. https://doi.org/10.1109/TCE.2006.1649669
- B. Debnath, S. Subramanya, D. Du, D. J. Lilja, "Large Block CLOCK (LB-CLOCK): A Write Caching Algorithm for Solid State Disks," Proceedings of Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pp. 1-9, 2009.
- S.Y. Lee, H.K. Bahn, S. H. Noh, "Design of a Page Replacement Policy for Hybrid PCM and DRAM Memory," Journal of KIISE: Computer Systems and Theory, Vol. 39, No. 2, pp. 111-118 2012 (in Korean).
- Q. Wei, C. Chen, J. Yang, "CBM: A Cooperative Buffer Management for SSD," Proceedings of Mass Storage Systems and Technologies, pp. 1-12, 2014.
- D. Kang, S. Han, Y. Kim, Y. Eom, "CLOCKDNV: A Write Buffer Algorithm for Flash Storage Devices of Consumer Electronics," IEEE Transactions Consumer Electronics, Vol. 63, no. 1, pp. 85-91, 2017. https://doi.org/10.1109/TCE.2017.014700
- Z. Sun, B. Xiuyuan, H. Li, W.F. Wong, Z.L. Ong, X. Zhu, W. Wu, "Multi Retention Level STT-RAM Cache Designs With a Dynamic Refresh Scheme," Proceedings of Microarchitecture, pp. 328-338 2011.
- X. Dong, C. Xu, N. Jouppi, Y. Xie, "NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory," Proceedings of Emerging Memory Technologies, pp. 15-50, 2014.
- M.K. Qureshi, V. Srinivasan, J.A. Rivers, "Scalable High Performance Main Memory System Using Phase-Change Memory Technology," Proceedings of ACM SIGARCH Computer Architecture, pp. 24-33, 2009.
- S. Pelley, T.F. Wenisch, B.T. Gold, B. Bridge, “Storage Management in the NVRAM Era,” Proceedings of the VLDB Endowment, Vol. 7, No. 2, pp. 121-132, 2013. https://doi.org/10.14778/2732228.2732231
- Yuan Xie, "Emerging Memory Technologies Design, Architecture and Applications," Chapter 1, Springer, 2014
- H.-S. P. Wong, C. Ahn, J. Cao, H.-Y. Chen, S. W. Fong, Z. Jiang, C. Neumann, S. Qin, J. Sohn, Y. Wu, S. Yu, X. Zheng, H. Li, J. A. Incorvia, S. B. Eryilmaz, K. Okabe, "Stanford Memory Trends," Avaliable: https://nano.stanford.edu/stanford-memory-trends, 2016.
- N. Agrawal, V. Prabhakaran, T. Wobber, J.D. Davis, M.S. Manasse, R. Panigrahy, "Design tradeoffs for SSD performance," Proceedings of USENIX Annual Technical Conference on Annual Technical Conference, Vol. 57, pp. 57-70, 2008.