The Journal of Korean Institute of Electromagnetic Engineering and Science (한국전자파학회논문지)

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
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Design of 94-GHz High-Gain Differential Low-Noise Amplifier Using 65-nm CMOS

65-nm CMOS 공정을 이용한 94 GHz 고이득 차동 저잡음 증폭기 설계

  • Seo, Hyun-woo (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Park, Jae-hyun (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kim, Jun-seong (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kim, Byung-sung (College of Information & Communication Engineering, Sungkyunkwan University)
  • 서현우 (성균관대학교 정보통신대학) ;
  • 박재현 (성균관대학교 정보통신대학) ;
  • 김준성 (성균관대학교 정보통신대학) ;
  • 김병성 (성균관대학교 정보통신대학)
  • Received : 2018.03.12
  • Accepted : 2018.04.30
  • Published : 2018.05.31
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Abstract

Herein, a 94-GHz low-noise amplifier (LNA) using the 65-nm CMOS process is presented. The LNA is composed of a four-stage differential common-source amplifier and impedance matching is accomplished with transformers. The fabricated LNA chip shows a peak gain of 25 dB at 94 GHz and has a 3-dB bandwidth at 5.5 GHz. The chip consumes 46 mW of DC power from a 1.2-V supply, and the total chip area, including the pads, is $0.3mm^2$.

본 논문은 65-nm 저전력 CMOS 공정을 이용해 94 GHz 대역 저잡음 증폭기를 설계한 결과를 제시한다. 설계한 저잡음 증폭기는 4단 차동 공통소스 구조를 가지며, 트랜스포머를 사용해 각 단 및 입출력 임피던스 정합 회로를 구성했다. 제작한 저잡음 증폭기는 94 GHz에서 최대 전력 이득 25 dB을 보이며, 3-dB 대역폭은 5.5 GHz이다. 제작한 칩의 면적은 패드를 포함해 $0.3mm^2$이며, 1.2 V 공급 전원에서 46 mW의 전력을 소비한다.

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References

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