The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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A Study on Elimination Solution of Parasitic Effect to Improve Area Efficiency and Frequency Stability of Relaxation Oscillator

이완 발진기의 면적 효율성과 주파수 안정성 향상을 위한 기생성분 효과 제거 기법연구

  • Received : 2017.11.02
  • Accepted : 2018.03.16
  • Published : 2018.04.01
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Abstract

In order to generate a clock source with low cost and high performance in system on chip(SoC), a relaxation oscillator with stable output characteristics according to PVT(process, voltage and temperature) fluctuation require a low area and a low power. In this paper, we propose a solution to reduce the current loss caused by parasitic components in the conventional relaxation oscillator. Since the slew rate of the bias current and the capacitor are adjusted to be the same through the proposed solution, a relaxation oscillator with low area characteristics is designed for the same clock source frequency implementation. The proposed circuit is designed using the TSMC CMOS 0.18um process. The Simulation results show that the relaxation oscillator using the proposed solution can prevent the current loss of about $279{\mu}A$ and reduce the total chip area by 20.8% compared with the conventional oscillator in the clock source frequency of 96 MHz.

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References

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