Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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An Integrated Cryptographic Processor Supporting ARIA/AES Block Ciphers and Whirlpool Hash Function

ARIA/AES 블록암호와 Whirlpool 해시함수를 지원하는 통합 크립토 프로세서 설계

  • Received : 2018.03.08
  • Accepted : 2018.03.14
  • Published : 2018.03.31
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Abstract

An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.

ARIA, AES 블록암호와 Whirlpool 해시함수를 단일 하드웨어 구조로 통합하여 효율적으로 구현한 크립토 프로세서에 대해 기술한다. ARIA, AES, Whirlpool의 알고리듬 특성을 기반으로 치환계층과 확산계층의 하드웨어 자원이 공유되도록 설계를 최적화하였다. Whirlpool 해시의 라운드 변환과 라운드 키 확장을 위해 라운드 블록이 시분할 방식으로 동작하도록 설계하였으며, 이를 통해 하드웨어 경량화를 이루었다. ARIA-AES-Whirlpool 통합 크립토 프로세서는 Virtex5 FPGA에 구현하여 하드웨어 동작을 검증하였으며, $0.18{\mu}m$ CMOS 셀 라이브러리로 합성한 결과 68,531 GE로 구현되었다. 80 MHz 클록 주파수로 동작하는 경우에, ARIA, AES 블록암호는 각각 602~787 Mbps, 682~930 Mbps, 그리고 Whirpool 해시는 512 Mbps의 성능을 갖는 것으로 예측되었다.

Keywords

References

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