마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제25권4호
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  • Pages.59-66
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  • 2018
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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반도체 패키지용 PCB의 구조 모델링 방법에 따른 패키지의 warpage 수치적 연구

Numerical Study on Package Warpage as Structure Modeling Method of Materials for a PCB of Semiconductor Package

  • 투고 : 2018.09.20
  • 심사 : 2018.12.13
  • 발행 : 2018.12.31
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초록

본 논문에서는 수치해석을 사용하여 반도체용 패키지에 적용된 인쇄회로기판 (PCB(printed circuit board)) 구조를 다층 구조의 소재 특성을 모델링한 것과 단일 구조라고 가정한 모델링을 적용하여 warpage를 해석함으로써 단일 구조 PCB 모델링의 유용성을 분석하였다. 해석에는 3층과 4층 회로층을 갖는 PCB가 사용되었다. 또한 단일 구조 PCB의 재료 특성값을 얻기 위해 실제 제품을 대상으로 측정을 수행하였다. 해석 결과에 의하면 PCB를 다층 구조로 모델링한 경우에 비해 단일 구조로 모델링한 경우에 warpage가 증가하여 PCB 구조의 모델링에 따른 warpage 분석결과가 분명한 유의차가 있었다. 또한, PCB의 회로층이 증가하면 PCB의 기계적 특성인 탄성계수와 관성모멘트가 증가하여 패키지의 warpage가 감소하였다.

In this paper, we analyzed the usefulness of single-structured printed circuit board (PCB) modeling by using numerical analysis to model the PCB structure applied to a package for semiconductor purposes and applying modeling assuming a single structure. PCBs with circuit layer of 3rd and 4th were used for analysis. In addition, measurements were made on actual products to obtain material characteristics of a single structure PCB. The analysis results showed that if the PCB was modeled in a single structure compared to a multi-layered structure, the warpage analysis results resulting from modeling the PCB structure would increase and there would be a significant difference. In addition, as the circuit layer of the PCB increased, the mechanical properties of the PCB, the elastic coefficient and inertia moment of the PCB increased, decreasing the package's warpage.

키워드

MOKRBW_2018_v25n4_59_f0001.png 이미지

Fig. 2. Finite element modeling of package for semiconductor with three layered PCB.

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Fig. 1. Package geometries for semiconductor with a three and a four layered PCB.

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Fig. 3. Finite element modeling of package for semiconductor with four layered PCB.

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Fig. 4. Finite element modeling of a layered PCB and a solid PCB for package.

MOKRBW_2018_v25n4_59_f0005.png 이미지

Fig. 5. Material properties of solder joints and a chip.

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Fig. 6. Specimens for material characteristics measuring of a solid PCB.

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Fig. 7. Material properties of a three layered solid PCB.

MOKRBW_2018_v25n4_59_f0008.png 이미지

Fig. 8. Material properties of a four layered solid PCB.

MOKRBW_2018_v25n4_59_f0009.png 이미지

Fig. 9. Cool down temperature condition.

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Fig. 10. Warpage distribution of package with three layered PCB and a solid PCB.

MOKRBW_2018_v25n4_59_f0011.png 이미지

Fig. 11. Gap of material properties between Mold+chip and a three layered PCB.

MOKRBW_2018_v25n4_59_f0012.png 이미지

Fig. 12. Warpage distribution of package with four layered PCB and a solid PCB.

MOKRBW_2018_v25n4_59_f0013.png 이미지

Fig. 13. Gap of material properties between Mold+chip and a four layered PCB.

MOKRBW_2018_v25n4_59_f0014.png 이미지

Fig. 14. Elastic modulus and moment inertia of PCB.

Table 1. Material properties of package for semiconductor.

MOKRBW_2018_v25n4_59_t0001.png 이미지

참고문헌

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