Journal of Electrical Engineering and Technology

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지
DOI QR코드

DOI QR Code

Electrical Characteristics of SiC Lateral P-i-N Diodes Fabricated on SiC Semi-Insulating Substrate

  • Kim, Hyoung Woo (Power Semiconductor Research Center at KERI) ;
  • Seok, Ogyun (Power Semiconductor Research Center at KERI) ;
  • Moon, Jeong Hyun (Power Semiconductor Research Center at KERI) ;
  • Bahng, Wook (Power Semiconductor Research Center at KERI) ;
  • Jo, Jungyol (Dept. of Electrical and Computer Engineering, Ajou University)
  • Received : 2017.07.11
  • Accepted : 2017.08.04
  • Published : 2018.01.01
Download PDF
⟨ Previous Next ⟩

Abstract

Static characteristics of SiC (silicon carbide) lateral p-i-n diodes implemented on semi-insulating substrate without an epitaxial layer are inVestigated. On-axis SiC HPSI (high purity semi-insulating) and VDSI (Vanadium doped semi-insulating) substrates are used to fabricate the lateral p-i-n diode. The space between anode and cathode ($L_{AC}$) is Varied from 5 to $20{\mu}m$ to inVestigate the effect of intrinsic-region length on static characteristics. Maximum breakdown Voltages of HPSI and VDSI are 1117 and 841 V at $L_{AC}=20{\mu}m$, respectiVely. Due to the doped Vanadium ions in VDSI substrate, diffusion length of carriers in the VDSI substrate is less than that of the HPSI substrate. A forward Voltage drop of the diode implemented on VDSI substrate is 12 V at the forward current of $1{\mu}A$, which is higher than 2.5 V of the diode implemented on HPSI substrate.

Keywords

E1EEFQ_2018_v13n1_387_f0001.png 이미지

Fig. 1. (a) Cross-sectional view and (b) top-view of thelateral p-i-n diode

E1EEFQ_2018_v13n1_387_f0002.png 이미지

Fig. 2. Simulated breakdown voltages as a function ofdiode length (LAC)

E1EEFQ_2018_v13n1_387_f0003.png 이미지

Fig. 3. Surface electric field distributions simulated atVanode = -300 V

E1EEFQ_2018_v13n1_387_f0004.png 이미지

Fig. 4. Forward characteristics of the device simulationresults

E1EEFQ_2018_v13n1_387_f0005.png 이미지

Fig. 5. Reverse I-V characteristics of lateral p-i-n diodesimplemented on (a) HPSI and (b) VDSI substrate

E1EEFQ_2018_v13n1_387_f0006.png 이미지

Fig. 6. Measured and simulated breakdown voltage as afunction of LAC

E1EEFQ_2018_v13n1_387_f0007.png 이미지

Fig. 7. Forward I-V characteristics of the device imple-mented on (a) HPSI and (b) VDSI

Table 1. Device parameters used in fabrication

E1EEFQ_2018_v13n1_387_t0001.png 이미지

References

  1. M. Bhatnagar and B. J. Baliga, "Comparison of 6HSiC, 3C-SiC, and Si for power devices," IEEE Trans. ED, vol. 40, no. 3, pp. 645-655, 1993. https://doi.org/10.1109/16.199372
  2. R. J. Trew, H. B. Yan, and P. M. Mock, "The potential of diamond and SiC electronic devices for microwave and millimeter-wave power applications," Proc. IEEE, vol. 79, pp. 598-620, 1991. https://doi.org/10.1109/5.90128
  3. W. S. Lee, K. W. Chu, C. F. Huang, L. S. Lee, M, J. Tsai, K. Y. Lee and F. Zhao, "Design and Fabrication of 4H-SiC Lateral High-Voltage Devices on a Semi- Insulating Substrate," IEEE Trans. ED, vol. 59, no. 3, pp. 754-760, 2012. https://doi.org/10.1109/TED.2011.2178028
  4. M. Noborio, J. Suda, and T. Kimoto, "4H-SiC lateral double RESURF MOSFETs with low on resistance," IEEE Trans. ED, vol. 54, no. 5, pp. 1216-1223, 2007. https://doi.org/10.1109/TED.2007.894249
  5. Y. Zhang, K. Sheng, M. Su, J. Zhao, P. Alexandrov, and L. Fursin, "1000 V 9.1 m$\Omega$cm2 normally off 4H-SiC lateral RESURF JFET for power integrated circuit applications," IEEE EDL, vol. 28, no. 5, pp. 404-407, 2008.
  6. C. F. Huang, J. R. Kuo, and C. C. Tsai, "High Voltage (3130V) 4H-SiC Lateral p-n Diodes on a Semi insulating Substrate," IEEE EDL, vol. 29, no. 1, pp. 83-85, 2008. https://doi.org/10.1109/LED.2007.910756
  7. W. S. Lee, C. W. Lin, M. H. Yang, C. F. Huang, J. Gong and Z. Feng, "Demonstration of 3500-V 4HSiC Lateral MOSFETs," IEEE EDL, vol. 32, no. 3, pp. 360-362, 2011. https://doi.org/10.1109/LED.2010.2101041
  8. Silvaco TCAD, ATLAS, Silvaco International Co. USA
  9. W. C. Mitchel, W. D. Mitchell, G. Landis, H. E. Smith, W. Lee and M. E. Zvanut, "Vanadium donor and acceptor levels in semi-insulating 4H- and 6HSiC," J. Appl. Phys., 101, 013707, 2007. https://doi.org/10.1063/1.2407263
  10. W. C. Mitchel and W. D. Mitchell, "Compensation mechanism in high purity semi-insulating 4H-SiC," J. Appl. Phys., 101, 053716, 2007. https://doi.org/10.1063/1.2437677
  11. T. Dalibor, G. Pensl, H. Matsunami, T. Kimoto, W. J. Choyke, A. Schoner, and N. Nordell, "Deep Defect Centers in Silicon Carbide Monitored with Deep Level Transient Spectroscopy," Phys. Stat. Sol. (a), 162, pp. 199-225, 1997. https://doi.org/10.1002/1521-396X(199707)162:1<199::AID-PSSA199>3.0.CO;2-0
  12. J. A. Appels and H. M. J. Vaes, "High voltage thin layer devices (RESURF DEVICES)," IEEE IEDM Tech. Dig., pp. 238-241, 1979.
  13. T. Kimoto, J. A. Cooper, "Fundamentals of silicon carbide technology," Wiley & Sons, Singapore, 2014, chap. 10 and app. C.
  14. A. O. Konstantinov, Q. Wahab, N. Nordell and U. Lindefelt, "Ionization rate and critical fields in 4H silicon carbide," Appl. Phys. Lett., vol. 71, no. 1, pp. 90- 92, 1997. https://doi.org/10.1063/1.119478
  15. M. V. S. Chandrashekhar, I. Chowdhury, P. Kaminski, R. Kozlowski, P. B. Klein, and T. Sudarshan, "High Purity Semi-Insulating 4H-SiC Epitaxial Layers by Defect-Competition Epitaxy: Controlling Si Vacancies," Appl. Phys. Express, vol. 5, 025502, 2012. https://doi.org/10.1143/APEX.5.025502
  16. A. Jain, P. Jumar, S. C. Jain, and V. Kumar, R. Kaur, R. M. Mehra, "Trap filled limit voltage (VTFL) and V2 law in space charge limited currents," J. Appl. Phys., 102, 094505, 2007. https://doi.org/10.1063/1.2802553