Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Optimization of Ar Reshape Process for 4H-SiC Trench MOSFET

4H-SiC Trench MOSFET 응용을 위한 Ar Reshape 공정 최적화

  • Sung, Min-Je (National Institute for Nanomaterials Technology, Pohang University of Science and Technology (POSTECH)) ;
  • Kang, Min-Jae (National Institute for Nanomaterials Technology, Pohang University of Science and Technology (POSTECH)) ;
  • Kim, Hong-Ki (National Institute for Nanomaterials Technology, Pohang University of Science and Technology (POSTECH)) ;
  • Kim, Seong-jun (National Institute for Nanomaterials Technology, Pohang University of Science and Technology (POSTECH)) ;
  • Lee, Jung-Yoon (National Institute for Nanomaterials Technology, Pohang University of Science and Technology (POSTECH)) ;
  • Lee, Wonbeom (National Institute for Nanomaterials Technology, Pohang University of Science and Technology (POSTECH)) ;
  • Lee, Nam-suk (National Institute for Nanomaterials Technology, Pohang University of Science and Technology (POSTECH)) ;
  • Shin, Hoon-Kyu (National Institute for Nanomaterials Technology, Pohang University of Science and Technology (POSTECH))
  • Received : 2018.12.08
  • Accepted : 2018.12.23
  • Published : 2018.12.31
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Abstract

For 4H-SiC trench MOSFET which can reduce on-resistance and switching losses compared to 4H-SiC planar MOSFET, the optimization study for decrease of sub-trench was carried out. In order to decrease sub-trench, Ar reshape process was used and trench shapes were observed as a function of temperature and process time. As a result, it was confirmed that the process conditions for $1500^{\circ}C$ and 20 min were most effective for the suitable trench profiles. In addition, dry/wet oxidation was performed at the Ar reshaped-samples to observe the oxidation thickness with different crystal orientations.

본 논문에서는 planar MOSFET 대비 on 저항 감소 및 스위칭 속도 개선의 장점이 있는 4H-SiC trench MOSFET응용을 위하여 trench MOSFET 중요 이슈 중 하나인 sub-trench의 개선연구를 수행하였다. sub-trench의 제거를 위하여 Ar reshape 공정을 수행하였고, 온도와 공정시간을 변화해가며 trench 형태의 변화를 관찰하였다. 그 결과 $1500^{\circ}C$, 20분 조건에서 가장 적절한 sub-trench 완화를 확인하였다. 또한 Ar reshape 공정 이후 건식/습식 산화공정을 진행하여 결정방향에 따른 산화막 두께변화에 대해 확인하였다.

Keywords

JGGJB@_2018_v22n4_1234_f0001.png 이미지

Fig. 1. Procedures of trench etching. 그림 1. 트렌치 에칭 과정

JGGJB@_2018_v22n4_1234_f0002.png 이미지

Fig. 2. SEM images for (a) as-etched sample and (b) Ar reshaped sample for 30 min at 1700℃, respectively. 그림 2. (a) Ar reshape 공정 전 샘플 및 (b) 1700℃ 30분 조건 Ar reshape 공정 샘플의 SEM 이미지

JGGJB@_2018_v22n4_1234_f0003.png 이미지

Fig. 3. SEM images for 10 min Ar reshaped samples at (a) 1100℃, (b) 1300℃, (c) 1400℃, (d) 1500℃, and (e) 1600℃, respectively. 그림 3. 10분 동안 Ar reshape한 샘플의 SEM 이미지. (a) 1100℃, (b) 1300℃, (c) 1400℃, (d) 1500℃, (e) 1600℃.

JGGJB@_2018_v22n4_1234_f0004.png 이미지

Fig. 4. SEM images for 20 min Ar reshaped samples at (a) 1400℃, (b) 1500℃, and (c) 1600℃, respectively. SEM images for dry/wet oxidation and poly-Si deposition by LPCVD on Ar reshaped samples at (d) 1400℃, (e) 1500℃, and (f) 1600℃, respectively. 그림 4. 20분 동안 Ar reshape한 샘플의 SEM 이미지. (a) 1400℃, (b) 1500℃, (c) 1600℃. 건식/습식 산화공정 및 poly-Si LPCVD성장한 샘플의 SEM 이미지. (d) 1400℃, (e) 1500℃, (f) 1600℃.

JGGJB@_2018_v22n4_1234_f0005.png 이미지

Fig. 5. SEM images for (a) as-etched sample and (b) sample after Ar reshape process, respectively. 그림 5. (a) Ar reshape 공정 전, (b) Ar reshape 공정 후의 샘플의 SEM 이미지

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