Fig. 1. Example of CRC code calculation. 그림 1. CRC 부호 계산 예제
Fig. 2. Serial CRC hardware based on LFSR [2]. 그림 2. LFSR 기반의 직렬 CRC 하드웨어 [2]
Fig. 3. Update process of function A4 and B4. 그림 3. A4, B4의 업데이트 과정
Fig. 4. 4bit-parallel Look-Ahead CRC Hardware. 그림 4. 4bit 병렬 Look-Ahead CRC 하드웨어
Fig. 5. HDL Code generation algorithm. 그림 5. HDL 코드 생성 알고리즘
Fig. 6. CRC Hardware HDL code generator. 그림 6. CRC 하드웨어 HDL 코드 생성기
Table 1. Equivalent gate counts of CRC hardware. 표 1. CRC 하드웨어의 등가 2 입력 NAND 게이트 수
References
- W. W. Peterson and D. T. Brown, "Cyclic Codes for Error Detection," Proceedings of the IRE, vol.49, 228-235, 1961. DOI:10.1109/JRPROC.1961.287814
- G. Campobello et al. "Parallel CRC realization," IEEE Trans. on Computers vol.52, 1312-1319, 2003. DOI:10.1109/TC.2003.1234528
- J. Jung et al, "Efficient Parallel Architecture for Linear Feedback Shift Regsiters," IEEE Trans. on Circuits and Sys. II - Express Brief, vol.62, no.11, 2015. DOI:10.1109/TCSII.2015.2456294
- G. Albertango and R. Sisto, "Parallel CRC Generation," IEEE Micro, vol.10, no.5, 1990. DOI:10.1109/40.60527
- E. Stavinov, "A Parallel CRC Generation Method," Circuits Celler Magzines for Computers, 2010.
- T. B. Pei, C. Zukowski, "High-speed parallel CRC circuits in VLSI," IEEE Trans. on Communications, vol.40, 653-657, 1992. DOI:10.1109/26.141415
- M. Walma, "Pipelined Cyclic Redundancy Check (CRC) Calculation," 2007 16th International Conference on Computer Communications and Networks, pp. 365-370, 2007. DOI:10.1109/ICCCN.2007.4317846
- C. Condo, M. Martina, G. Piccinini and G. Masera, "Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced," IEEE Signal Processing Letters, vol.21, no.11, pp.1380-1384, 2014. DOI:10.1109/LSP.2014.2334393
- C. Cheng and K. K. Parhi, "High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.53, no.10, pp.1017-1021, 2006. DOI:10.1109/TCSII.2006.882213
- M. Ayinala and K. K. Parhi, "High-Speed Parallel Architectures for Linear Feedback Shift Registers," IEEE Transactions on Signal Processing, vol.59, no.9, pp.4459-4469, 2011. DOI:10.1109/TSP.2011.2159495