한국전자통신학회논문지 (The Journal of the Korea institute of electronic communication sciences)

한국전자통신학회 (Korea Institute of Electronic Communication Science)
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메모리 소자의 셀 커패시턴스에 미치는 공정 파라미터 해석

Analysis of Process Parameters on Cell Capacitances of Memory Devices

  • 정윤근 (전남대학교 기계설계공학부) ;
  • 강성준 (전남대학교 전기및반도체공학과) ;
  • 정양희 (전남대학교 전기및반도체공학과)
  • 투고 : 2017.08.30
  • 심사 : 2017.10.18
  • 발행 : 2017.10.31
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초록

본 연구에서는 DRAM 커패시터의 유전막 박막화를 위한 Load Lock(L/L) LPCVD 시스템을 이용한 적층형 커패시터의 제조 공정이 셀 커패시턴스에 미치는 영향을 조사하였다. 그 결과 기존의 non-L/L 장치에 비하여 약 $6{\AA}$의 산화막 유효두께를 낮춤으로 커패시턴스로 환산 시 약 3-4 fF의 차이가 나타남을 확인할 수 있었다. 또한 절연막으로써 질화막 두께의 측정 범위가 정상적인 관리 범위의 분포임에도 불구하고 Cs는 계산치보다 약 3~6 fF 정도 낮은 것으로 확인되었다. 이는 node poly FI CD가 spec 상한치로 관리되어 셀 표면적의 감소를 초래하였고 이는 약 2fF의 Cs 저하를 나타내었다. 따라서 안정적인 Cs의 확보를 위해서는 절연막의 두께 및 CD 관리를 spec 중심값의 10 % 이내로 관리할 필요가 있음을 확인하였다.

In this study, we investigated the influence of the fabrication process of stacked capacitors on the cell capacitance by using Load Lock (L/L) LPCVD system for dielectric thin film of DRAM capacitor. As a result, it was confirmed that the capacitance difference of about 3-4 fF is obtained by reducing the effective thickness of the oxide film by about $6{\AA}$ compared to the conventional non-L/L device. In addition, Cs was found to be about 3-6 fF lower than the calculated value, even though the measurement range of the thickness of the nitride film as an insulating film was in a normal management range. This is because the node poly FI CD is managed at the upper limit of the spec, resulting in a decrease in cell surface area, which indicates a Cs reduction of about 2fF. Therefore, it is necessary to control the thickness of insulating film and CD management within 10% of the spec center value in order to secure stable Cs.

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참고문헌

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