전기학회논문지 (The Transactions of The Korean Institute of Electrical Engineers)

  • 제66권10호
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  • Pages.1494-1498
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  • 2017
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  • 1975-8359(pISSN)
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  • 2287-4364(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
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Gate Overlap에 따른 나노선 CMOS Inverter 특성 연구

Characteristics of Nanowire CMOS Inverter with Gate Overlap

  • Yoo, Jeuk (Dept. of Electrical Engineering, Korea University) ;
  • Kim, Yoonjoong (Dept. of Electrical Engineering, Korea University) ;
  • Lim, Doohyeok (Dept. of Electrical Engineering, Korea University) ;
  • Kim, Sangsig (Dept. of Electrical Engineering, Korea University)
  • 투고 : 2017.05.02
  • 심사 : 2017.09.22
  • 발행 : 2017.10.01
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초록

In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage ($V_{dd}$) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high $I_{on}/I_{off}$ ratios are major factors that enable the excellent operation of the logic gate.

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참고문헌

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