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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Hardware Implementation of Context Modeler in HEVC CABAC Decoder

HEVC CABAC 복호기의 문맥 모델러 설계

  • Kim, Sohyun (School of Electronic Engineering, Soongsil University) ;
  • Kim, Doohwan (School of Electronic Engineering, Soongsil University) ;
  • Lee, Seongsoo (School of Electronic Engineering, Soongsil University)
  • Received : 2017.09.18
  • Accepted : 2017.09.28
  • Published : 2017.09.30
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Abstract

HEVC (high efficiency video coding) exploits CABAC (context-based adaptive binary arithmetic coding) for entropy coding, where a context model estimates the probability for each syntax element. In this paper, a context modeler was designed and implemented for CABAC decoding. lookup table was used to reduce computation and to increase speed. 12 simulations for HEVC standard test sequences and encoder configurations were performed, and the context modeler was verified to perform correction operations. The designed context modeler was synthesized in 0.18um technology. Maximum frequency, maximum throughput, and gate count are 200 MHz, 200 Mbin/s, and 29,268 gates, respectively.

HEVC(high efficiency video coding)의 엔트로피 코딩 방식인 CABAC(context-based adaptive binary arithmetic coding)에서는 각 구문 요소의 발생 확률을 추정하는 문맥 모델이 사용된다. 본 논문에서는 CABAC 복호화에 필요한 문맥 모델러를 설계하고 이를 구현하였다. 초기화에 필요한 연산 숫자를 줄이고 속도를 높이기 위해 참조 테이블을 사용하였으며, HEVC의 표준 테스트 영상 및 표준 부호기 구성에 대해 12가지의 시뮬레이션을 수행하여 모두 성공적으로 동작하는 것을 확인하였다. 설계된 문맥 모델러를 0.18um에서 합성하였을 때의 최대 동작 주파수, 최대 처리율 및 게이트 수는 각각 200 MHz, 200 Mbin/s, 29,268 게이트이다.

Keywords

References

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