JSTS:Journal of Semiconductor Technology and Science

  • 제17권4호
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  • Pages.568-576
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  • 2017
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A Clock and Data Recovery Circuit with Adaptive Loop Bandwidth Calibration and Idle Power Saved Frequency Acquisition

  • Lee, Won-Young (Department of Electronic IT Media Engineering, Seoul National University of Science and Technology (SeoulTech)) ;
  • Jung, Chae Young (Department of Electronic IT Media Engineering, Seoul National University of Science and Technology (SeoulTech)) ;
  • Cho, Ara (Department of Electronic IT Media Engineering, Seoul National University of Science and Technology (SeoulTech))
  • 투고 : 2017.06.30
  • 심사 : 2017.08.10
  • 발행 : 2017.08.30
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초록

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

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참고문헌

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