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LASPI: 지원점 보간법을 이용한 H/W 구현에 용이한 스테레오 매칭 방법

LASPI: Hardware friendly LArge-scale stereo matching using Support Point Interpolation

  • 박상현 (한국외국어대학교 컴퓨터 및 정보통신공학과) ;
  • 기미레 디팍 (전자부품연구원 모빌리티플랫폼연구센터) ;
  • 김정국 (한국외국어대학교 컴퓨터전자시스템공학부) ;
  • 한영기 ((주)아르고 ASIC 개발팀)
  • 투고 : 2017.05.02
  • 심사 : 2017.06.15
  • 발행 : 2017.09.15

초록

논문에서는 정류(Rectification), 디스패리티 추정(Disparity Estimation) 및 시각화를 포함한 스테레오 비전 프로세싱 시스템의 새로운 하드웨어 및 소프트웨어 아키텍처를 개발하였다. 개발된 지원점 보간법을 이용한 대형 스테레오 매칭 방법(LASPI)은 고화질 이미지의 지원점 밀도가 높은 영역에서의 디스패리티 매칭에 있어, ELAS 등 기존 스테레오 매칭 방법과 비교할 때, 디스패리티 맵에 대한 품질 수준을 유지하면서도 실시간 성능 지원 측면에서 우수하다. LASPI는 자율주행 자동차에 적용되는 장애물 인식 시스템, 거리 검출 시스템, 장애물 검출 시스템 등, 안전에 민감한 모듈 적용을 위해, 프레임 처리속도의 실시간성, 거리 값 분해 성능의 정확성, 낮은 리소스 사용 등, 요구조건을 충족하도록 설계 되었다. 개발된 LASPI 알고리즘은 H/W 병렬처리 구조와 4 단계 파이프라인으로 구성된 FPGA로 구현되었다. 148.5MHz 클럭의 Xilinx Virtex-7 FPGA 기반으로 구현된 시스템은 각종 실험을 통해, HD급 이미지 ($1280{\times}720$ 픽셀)에 대해 실차에 응용 가능한 디스패리티 맵을 산출하면서도 실시간 처리 요구 조건인 초당 30 프레임 처리가 가능함을 확인하였다.

In this paper, a new hardware and software architecture for a stereo vision processing system including rectification, disparity estimation, and visualization was developed. The developed method, named LArge scale stereo matching method using Support Point Interpolation (LASPI), shows excellence in real-time processing for obtaining dense disparity maps from high quality image regions that contain high density support points. In the real-time processing of high definition (HD) images, LASPI does not degrade the quality level of disparity maps compared to existing stereo-matching methods such as Efficient LArge-scale Stereo matching (ELAS). LASPI has been designed to meet a high frame-rate, accurate distance resolution performance, and a low resource usage even in a limited resource environment. These characteristics enable LASPI to be deployed to safety-critical applications such as an obstacle recognition system and distance detection system for autonomous vehicles. A Field Programmable Gate Array (FPGA) for the LASPI algorithm has been implemented in order to support parallel processing and 4-stage pipelining. From various experiments, it was verified that the developed FPGA system (Xilinx Virtex-7 FPGA, 148.5MHz Clock) is capable of processing 30 HD ($1280{\times}720pixels$) frames per second in real-time while it generates disparity maps that are applicable to real vehicles.

키워드

참고문헌

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