References
- R. G. Gallager, "Low-density parity-check codes," IRE Trans. Information Theory, vol. 8, no. 1, pp. 21-28, Jan. 1962. https://doi.org/10.1109/TIT.1962.1057683
- ETSI, "Digital Video Broadcasting (DVB); Second Generation Framing Structure, Channel Coding and Modulation Systems for Broadcasting, Interactive Services, News Gathering and other Broadband Satellite Applications," EN 302 307, V1. 1. 1, Jun. 2004.
- W. Liang, W. Zhang, D. He, Y. Guan, Y. Wang, and J. Sun, "Digital Terrestrial Television Broadcasting in China," IEEE MultiMedia, vol. 14, no. 3, pp. 92-97, July-Sept, 2007. https://doi.org/10.1109/MMUL.2007.47
- IEEE P802.11n/TM-2009, "IEEE standard for information technology part 11: wireless LAN medium access control (MAC) and physical layer (PHY) specifications," Oct. 2009.
- D. Qu, L. Li, and T. Jiang, "Invertible subset LDPC code for PAPR reduction in OFDM systems with low complexity," IEEE Transactions on Wireless Communications, vol. 13, no. 4, pp. 2204 - 2213, Apr. 2014. https://doi.org/10.1109/TWC.2014.031314.131289
- L. Li, D. Qu, and T. Jiang, "Partition optimization in LDPC-coded OFDM systems with PTS PAPR reduction," IEEE Transactions on Vehicular Technology, vol. 63, no. 8, pp. 4108-4113, Oct. 2014. https://doi.org/10.1109/TVT.2014.2305153
- J. Kim and W. Sung, "Rate-0.96 LDPC decoding VLSI for soft-decision error correction of NAND flash memory," IEEE Trans. VLSI, vol. 22, no. 5, pp. 1004-1015, May 2014. https://doi.org/10.1109/TVLSI.2013.2265314
- L. Kong, J. Wen, G. Han, S. Zhao, M. Jiang, and C. Zhao, "Quantization and reliability-aware iterative majority-logic decoding algorithm for LDPC code in TLC NAND flash memory," in Proc. of 2016 8th International Conference on Wireless Communications & Signal Processing (WCSP), pp. 1-5, Oct. 2016.
- K.-C. Ho, C.-L. Chen, and H.-C. Chang, "A 520k (18900, 17010) array dispersion LDPC decoder architectures for NAND flash memory," IEEE Trans. Very Large Scale Integr. Syst., vol. 24, no. 4, pp. 1293-1304, Apr. 2016. https://doi.org/10.1109/TVLSI.2015.2464092
- J. Zhang, Y. Wang, M. Fossorier, and J. S. Yedidia, "Replica shuffled iterative decoding," IEEE Int. Symp. on Information Theory, Adelaide, Australia, pp. 454-458, Sep. 2005.
- J. H. Kim, M. Y. Nam, and H. Y. Song, "Variable-to-check residual belief propagation for LDPC codes," IET Electronics Letters, vol. 45, no. 2, pp. 117-118, Jan. 2009. https://doi.org/10.1049/el:20092505
- A. Anand and P. S. Kumar, "An efficient non binary LDPC decoder using layered dynamic scheduling," J. Comput. Theor. Nanosci., vol. 12, no. 12, pp. 5066-5070, Dec. 2015. https://doi.org/10.1166/jctn.2015.4476
- K. Zhao, Y. Xu, D. He, Y. Guan, and W. Zhang, "Variable LLR scaling in LDPC min-sum decoding under horizontal shuffled structure," in Proc. of 2016 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (BMSB), pp. 1-7, Jun. 2016.
- M. K. Roberts and R. Jayabalan, "An improved self adaptive min-sum decoding algorithm for flexible low-density parity-check decoder," Natl. Acad. Sci. Lett., pp. 1-5, Nov. 2016.
- J. Chen and M. Fossorier, "Near optimum universal belief propagation based decoding of low density parity check codes," IEEE Trans. Commun., vol. COM-50, no. 3, pp. 406-414, Mar. 2002.
- S. Kim, C. Park, and S. Hwang, "A novel partially parallel architecture for high-throughput LDPC decoder for DVB-S2," IEEE Trans. Consumer Electron., vol. 56, no. 2, pp. 820-825, May. 2010. https://doi.org/10.1109/TCE.2010.5506007
- R. Tanner, "A recursive approach to low complexity codes," IEEE Trans. Inform. Theory, vol. 27, no. 5, pp. 533-547, Sept. 1981. https://doi.org/10.1109/TIT.1981.1056404
- M. Jiang, C. Zhao, L. Zhang, and E. Xu, "Adaptive offset min-sum algorithm for low-density parity check codes," IEEE Commum. Lett.,vol. 10, no. 6, pp. 483-485, June 2006. https://doi.org/10.1109/LCOMM.2006.1638623
- J. Y. Park and K. S. Chung, "An adaptive low-power LDPC decoder using SNR estimation," EURASIP Journal on Wireless Communications and Networking, vol. 2011, no. 1, pp. 1-9, July 2011. https://doi.org/10.1186/1687-1499-2011-1
- C. K. Liau, S. Y. Lin, T. H. Tsai, and C. L. Wey, "A partially parallel low-density parity check code decoder with reduced memory for long code-length," in Proc. of 18th VLSI Des./CAD Symp., Hua-Lien, Taiwan, Aug. 2007.
- B. Xiang, R. Shen, A. Pan, D. Bao, and X. Zeng, "An area-efficient and low-power multirate decoder for quasi-cyclic low-density parity-check codes," IEEE Trans. Very Large Scale Integration Systems, vol. 18, no. 10, pp. 1447-1460, Sep. 2010. https://doi.org/10.1109/TVLSI.2009.2025169
- D. J. C. MacKay "Encyclopedia of sparse graph codes," Cavendish Laboratory, University of Cambridge, 2005.
- F. Kienle and N. Wehn, "Low complexity stopping criterion for LDPC code decoders," in Proc. of IEEE 61st Vehicular Technology Conference, Stockholm, Sweden, May 2005.
- C. L. Wey, M. D. Shieh, and S. Y. Lin, "Algorithms of finding the first two minimum values and their hardware implementation," IEEE Trans. Circuits Syst. I, vol. 55, no. 11, pp. 3430-3437, Dec. 2008. https://doi.org/10.1109/TCSI.2008.924892
Cited by
- A Weighted Block-by-Block Decoding Algorithm for CPM-QC-LDPC Code Using Neural Network vol.12, pp.8, 2017, https://doi.org/10.3837/tiis.2018.08.011