DOI QR코드

DOI QR Code

Characterization of the Vertical Position of the Trapped Charge in Charge-trap Flash Memory

  • Kim, Seunghyun (Department of Electrical and Computer Engineering with Inter-university Semiconductor Research Center (ISRC), Seoul National University) ;
  • Kwon, Dae Woong (Department of Electrical and Computer Engineering with Inter-university Semiconductor Research Center (ISRC), Seoul National University) ;
  • Lee, Sang-Ho (Department of Electrical and Computer Engineering with Inter-university Semiconductor Research Center (ISRC), Seoul National University) ;
  • Park, Sang-Ku (Department of Electrical and Computer Engineering with Inter-university Semiconductor Research Center (ISRC), Seoul National University) ;
  • Kim, Youngmin (Department of Electronics Engineering, Gachon University) ;
  • Kim, Hyungmin (Novachips) ;
  • Kim, Young Goan (Novachips) ;
  • Cho, Seongjae (Department of Electronics Engineering, Gachon University) ;
  • Park, Byung-Gook (Department of Electrical and Computer Engineering with Inter-university Semiconductor Research Center (ISRC), Seoul National University)
  • 투고 : 2016.07.26
  • 심사 : 2016.12.11
  • 발행 : 2017.04.30

초록

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

키워드

참고문헌

  1. D.-H. Kim, S. Cho, D. H. Li, J.-G. Yun, J. H. Lee, G. S. Lee, Y. Kim, W. B. Shim, S. H. Park, W. Kim, H. Shin, and B.-G. Park, "Program/erase model of nitride-based NAND-type charge trap flash memories," Jpn. J. Appl. Phys., vol. 49, no. 8R, 084301, Aug. 2010. https://doi.org/10.1143/JJAP.49.084301
  2. J. Fujiki, T. Haimoto, N. Yasuda, and M. Koyama, "Dynamics of the charge centroid in metal-oxide-nitride-oxide-silicon memory cells during avalanche injection and Fowler-Nordheim injection based on incremental-step-pulse programming," Jpn. J. Appl. Phys., vol. 50, no. 4S, 04DD06, Apr. 2011. https://doi.org/10.7567/JJAP.50.04DD06
  3. A. Padovani, L. Larcher, V. D. Marca, P. Pavan, H. Park, and G. Bersuker, "Charge trapping in alumina and its impact on the operation of metal-alumina-nitride-oxide-silicon memories: Experiments and simulations," J. Appl. Phys., vol. 110, no. 1, 014505, 2011. https://doi.org/10.1063/1.3602999
  4. A. Padovani, L. Larcher, and P. Pavan, "Compact modeling of TANOS program/erase operations for SPICE-like circuit simulations," Microelectron. J., vol. 44, no. 1, pp. 50-57, Jan. 2013. https://doi.org/10.1016/j.mejo.2011.07.017
  5. E. Vianello, F. Driussi, A. Arreghini, P. Palestri, D. Esseni, L. Selmi, N. Akil, M. J. van Duuren, and D. S. Golubovic, "Experimental and Simulation Analysis of program/retention transients in silicon nitride-based NVM cells," IEEE Trans. Electron Devices, vol. 56, pp. 1980-1990, Sep. 2009. https://doi.org/10.1109/TED.2009.2026113
  6. Sentaurus User's Manual, 2014.
  7. H.-T. Lue, S.-Y Wang, E.-K. Lai, Y.-H. Shih, S.-C. Lai, L.-W. Yang, K.-C. Chen, J. Ku, K.-Y. Hsieh, and C.-Y. Lu, "BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability," Tech. Dig. IEDM, Washington DC, USA, pp. 547-550, Dec. 2005.
  8. S. Cho, W. B. Shim, Y. Kim, J.-G. Yun, J. D. Lee, H. Shin, J.-H. Lee, and B.-G. Park, "A Charge Trap Folded NAND Flash Memory Device with Bandgap-Engineered Storage Node," IEEE Trans. Electron Devices, vol. 58, no. 2, pp.288-295, Feb. 2011. https://doi.org/10.1109/TED.2010.2090420
  9. Y. Kim, J.-G. Yun S. H. Park, W. Kim, J. Y. Seo, M. Kang, K.-C. Ryoo, J.-H. Oh, J.-H. Lee, H. Shin, and B.-G. Park, "Three-Dimensional NAND Flash Architecture Design Based on Single-Crystalline Structure Array," IEEE Trans. Electron Devices, vol. 59, no. 1, pp. 35-45, Jan. 2012. https://doi.org/10.1109/TED.2011.2170841
  10. S.-M. Joe, J.-H. Yi, S.-K. Park, H. Shin, B.-G. Park, Y. J. Park, and J.-H. Lee, "Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate NAND Flash Memory String," IEEE Trans. Electron Devices, vol. 58, no. 1, pp. 67-72, Jan. 2011. https://doi.org/10.1109/TED.2010.2088126
  11. W. Kim, J. H. Lee, J.-G. Yun, S. Cho, D.-H. Li, Y. Kim, D.-H. Kim, G. S. Lee, S.-H. Park, W. B. Shim, J.-H. Lee, H. Shin, and B.-G. Park, "Arch NAND Flash Memory Array with Improved Virtual Source/Drain Performance," IEEE Electron Device Letters, vol. 31, no. 12, pp. 1374-1376, Dec. 2010. https://doi.org/10.1109/LED.2010.2074180
  12. A. Arreghini, F. Driussi, E. Vinaello, D. Esseni, M. J. van Duuren, D. S. Golubovic, N. Akil, and R. van Schaijk, "Experimental Characterization of the Vertical Position of the Trapped Charge in SiNbased Nonvolatile Memory Cells," IEEE Trans. Electron Devices, vol. 55, no. 5, pp. 1211-1219, May 2008. https://doi.org/10.1109/TED.2008.919713
  13. P.-Y. Du, H.-T. Lue, S.-Y. Wang, E.-K. Lai, T.-Y. Huang, K.-Y. Hsieh, R. Liu, and C.-Y Lu, "Study of the Gate-Sensing and Channel-Sensing Transient Analysis Method for Monitoring the Charge Vertical Location of SONOS-Type Devices," IEEE Trans. Device Mater. Reliab., vol. 7, no. 3, pp. 407-419, Sep. 2007. https://doi.org/10.1109/TDMR.2007.907290
  14. A. Arreghini, F. Driussi, D. Esseni, L. Selmi, M. J. van Duuren, and R. van Schaijk, "Experimental extraction of the charge centroid and of the charge type in the P/E operation of sonos memory cells," Tech. Dig. IEDM, San Francisco, CA, USA, pp. 11-13, Dec. 2006.