References
- P. Greisen, M. Runo, P. Guillet, S. Heinzle, A. Smolic, H. Kaeslin and M. Gross, "Evaluation and FPGE Implementation of Sparse Linear Solvers for Video Processing Applications", Circuits and Systems for Video Technology, IEEE, vol. 23, Issue: 8, pp. 1402-1407, Feb. 2013. DOI: https://doi.org/10.1109/TCSVT.2013.2244797
- UG1165 (v2015.3), "Zynq-7000 All Programmable SoC: Embedded Design Tutorial", Xilinx, Nov. 2015.
- DS190(v1.8), "Zynq-7000 All Programmable SoC Overview", Xilinx, May 2015.
- UG585(v1.10), " Zynq-7000 All Programmable SoC Technical Reference Manual", Xilinx, Feb. 2015.
- UG909(v2014.4), "Vivado Design Suite User Guide Partial Reconfiguration", Xilinx, Nov. 2014.
- E, Stott, P. Sedcole, P. Y. K. Cheung, "Fault tolerant methods for reliability in FPGAs", International Conference on Field Programmable Logic and Applications, pp. 415-420, Sept. 2008. DOI: https://doi.org/10.1109/fpl.2008.4629973
- Naveed Imran, Ronald F. DeMara, Jooheung Lee, Jian Huang, "Self-Adapting Resource Escalation for Resilient Signal Processing Architectures", Journal of Signal Processing Systems, vol. 77, no. 3, pp. 257-280, Dec. 2014. DOI: https://doi.org/10.1007/s11265-013-0811-x
- C. Insaurralde, "Reconfigurable computer architectures for dynamically adaptable avionics systems", IEEE Aerospace and Electronic Systems Magazine, vol. 30, pp. 46-53, Sept. 2015. DOI: https://doi.org/10.1109/MAES.2015.140077
- UG909(v2014.4), "Vivado Design Suite User Guide Partial Reconfiguration", Xilinx, Nov. 2014.
- Kizheppatt Vipin and Suhaib A. Fahmy, "ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq", Embedded Systems Letters, IEEE, vol. 6, Issue: 3, pp. 41-44, Sep. 2014. DOI: https://doi.org/10.1109/LES.2014.2314390
- XAPP1159(v1.0), Christian Kohn, "Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 All Programmable SoC Devices", Xilinx, Jan. 2013.
- Soonjong Jin, Wonki Kim and Jechang Jeong, "Fine Directional De-interlacing Algorithm Using Modified Sobel operation", Consumer Electronics, IEEE, vol.54, Issue: 2, pp. 587-862, May. 2008. DOI: http://dx.doi.org/10.1109/TCE.2008.4560171
- Pei-Yin Chen, Chih-Yuan Lien, and Yi-Ming Lin, "A Real-time Image Denoising Chip", Circuits and Systems, ISCAS IEEE International Symposium on, pp. 3390-3393, May. 2008. DOI: http://dx.doi.org/10.1109/ISCAS.2008.4542186
- Chenglong Chen, Jiangqun Ni and Jiwu Huang, "Blind Detection of Median Filtering in Digital Images: A Difference Domain based Approach", Image Processing, IEEE, vol. 22, Issue: 12, pp. 4699-4710, Aug. 2013. DOI: https://doi.org/10.1109/TIP.2013.2277814
- William K. Pratt, "Digital Image Processing", PIKS Inside, Third Edition, pp. 490-494, Aug. 2000.
- XAPP1231 (v1.1), Christian Kohn, "Partial Reconfiguration of a Hardware Accelerator with Vivado Design Suite for Zynq-7000 Ap SoC Processor", Xilinx, Mar. 2015.
- UG821 (v12.0), "Zynq7000 All Programmable SoC Software Developers Guide", Xilinx, Sep. 2015.
- XAPP890 (v1.0), Fernando Martinez Vallina, Christian Kohn, and Pallav Joshi, "Zynq All Programmable SoC Sobel Filter Implementation Using the Vivado HLS Tool", Xilinx, Sep. 2012.
- UG902 (v2015.4), "Vivado Design Suite User Guide : High-Level Synthesis", Xilinx, Nov. 2015.
- Kizheppatt Vipin and Suhaib A. Fahmy, "ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq", IEEE Embedded Systems Letters, vol. 6, Issue : 3, Mar. 2014. DOI: http://dx.doi.org/10.1109/LES.2014.2314390
- Ikram E. Abdou and William K. Pratt, "Quantitative design and evaluation of enhancement/thresholding edge detectors", Proceedings of the IEEE , vol. 67 , no. 5, pp. 753-763, May 1979. DOI: https://doi.org/10.1109/PROC.1979.11325
- J.-A. Jiang, C.-L. Chuang, Y.-L. Lu and C.-S. Fahn, "Mathematical-morphology-based edge detectors for detection of thin edges in low-contrast regions", Image Processing, IET, vol. 1, no.3 pp. 269-277, Sep. 2007. DOI: https://doi.org/10.1049/iet-ipr:20060273
- UG907(v2015.4), "Vivado Design Suite User Guide: Power Analysis and Optimization", Xilinx, Nov. 2015.