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Design and Implementation of CAN IP using FPGA

FPGA를 이용한 CAN 통신 IP 설계 및 구현

  • Son, Yeseul (Department of Aerospace Information Engineering, Konkuk University) ;
  • Park, Jungkeun (Department of Aerospace Information Engineering, Konkuk University) ;
  • Kang, Taesam (Department of Aerospace Information Engineering, Konkuk University)
  • 손예슬 (건국대학교 항공우주정보시스템공학부) ;
  • 박정근 (건국대학교 항공우주정보시스템공학부) ;
  • 강태삼 (건국대학교 항공우주정보시스템공학부)
  • Received : 2016.04.18
  • Accepted : 2016.06.24
  • Published : 2016.08.01

Abstract

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

Keywords

References

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