The Journal of Korea Institute of Information, Electronics, and Communication Technology (한국정보전자통신기술학회논문지)

Korea Information Electronic Communication Technology (한국정보전자통신기술학회)
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Low Complexity Gradient Magnitude Calculator Hardware Architecture Using Characteristic Analysis of Projection Vector and Hardware Resource Sharing

정사영 벡터의 특징 분석 및 하드웨어 자원 공유기법을 이용한 저면적 Gradient Magnitude 연산 하드웨어 구현

  • Kim, WooSuk (Electrical, Electronic, and Control Engineering, HanKyong University) ;
  • Lee, Juseong (Center of Human-centered Interaction for Coexistence) ;
  • An, Ho-Myoung (Department of Electronics, Osan University)
  • Received : 2016.08.23
  • Accepted : 2016.08.25
  • Published : 2016.08.30
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Abstract

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

본 논문은 저면적 gradient magnitude 연산을 위한 하드웨어 구조를 제안한다. 하드웨어 복잡도를 줄이기 위해 정사영 벡터의 특징 및 하드웨어 자원 공유기법을 이용했다. 제안된 하드웨어 구조는 gradient magnitude 연산 알고리즘의 변형 없이 구현되었기 때문에 gradient magnitude 데이터 품질의 열화 없이 구현될 수 있다. 제안된 저면적 gradient magnitude 연산 하드웨어는 Altera Quartus II v15.0 환경에서 Altera Cyclone VI (EP4CE115F29C7N) FPGA를 이용하여 구현되었다. 구현 결과, 기존 하드웨어 구조를 이용하여 구현한 연산기와의 비교에서 15%의 logic elements 및 38%의 embedded multiplier 절감 효과가 있음을 확인했다.

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