Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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The Impedance Analysis of Multiple TSV-to-TSV

다중(multiple) TSV-to-TSV의 임피던스 해석

  • Lee, Sihyun (Department of Information and Communication Engineering, Dong Seoul University)
  • 이시현 (동서울대학교 정보통신과)
  • Received : 2016.05.13
  • Accepted : 2016.06.28
  • Published : 2016.07.25
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Abstract

In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.

본 논문에서는 기존의 2D IC의 성능을 개선하고 3D IC의 집적도와 전기적인 특성을 개선하기 위한 목적으로 연구되고 있는 TSV (Through Silicon Via)의 임피던스를 해석하였다. 향후 Full-chip 3D IC 시스템 설계에서 TSV는 매우 중요한 기술이며, 높은 집적도와 광대역폭 시스템 설계를 위해서 TSV에 대한 전기적인 특성에 관한 연구가 매우 중요하다. 따라서 본 연구에서는 Full-chip 3D IC를 설계하기 위한 목적으로 다중 TSV-to-TSV에서 거리와 주파수에 따른 TSV의 임피던스 영향을 해석하였다. 또한 이 연구 결과는 Full-chip 3D IC를 제조하기 위한 반도체 공정과 설계 툴에 적용할 수 있다.

Keywords

References

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