Failure Modes Classification and Countermeasures of Stacked IC Packages

적층 IC 패키지의 고장모드 분류와 대책

  • Song, G.H. (Department of Industrial Engineering, Ajou University) ;
  • Jang, J.S. (Department of Industrial Engineering, Ajou University)
  • Received : 2016.11.09
  • Accepted : 2016.12.23
  • Published : 2016.12.25

Abstract

Purpose: With the advance of miniaturization of electronic products, stacked packages of high density semiconductors are commonly used. Potential failure modes and mechanisms of stacked packages are identified. Methods: Failure modes and mechanisms of thin chip stacked packages are determined through the categorization and failure analysis: delamination, non-wet, crack, ESD, EMI and the process related damages. Results: Those failure modes are not easy to find and require excessive amount time and effort for analysis and subsequent improvement. Conclusion: In this study, a method of estimating the failure rate based on the strength measurement is suggested.

Keywords

References

  1. Ford (2011). "Failure Mode and Effects Analysis-FMEA Handbook ver 4.2". Ford.
  2. Jang, J. S. (2012). "Reliability Concept and Approach Method". Journal of the KSME, Vol. 7, No. 52, pp. 30-34.
  3. Kitano, M., Nishimura, A., Kawai, S. and Nishi, K. (1988). "Analysis of package cracking during reflow soldering process". 26th Annual Proceedings Reliability Physics Symposium, pp. 90-95.
  4. Lee, N. C. (2002). "Reflow Soldering Processes". Newnes.
  5. Kim, D. S., Hong, H. S., Park, H. M., Kim, J. H. and Joo, K. S. (2015). "Radiation Damage of Semiconductor Device by X-ray". Journal of Radiation Protection and Research, Vol. 40, No. 2, pp. 110-117. https://doi.org/10.14407/jrp.2015.40.2.110
  6. IPC/JEDEC (2015). "Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices". J-STD-020E.
  7. Lee, C. K., Loh, W. K., Ong, K. E. and Chin, I. (2006). "Study of Dynamic Warpage of Flip Chip Packages under Temperature Reflow". Electronics Manufacturing and Technology, 31st International Conference Petaling Jaya, pp. 185-190.
  8. Deel, K. V. (2013). "FCBGA Package Warpage". Yole, p. 3.
  9. Shen, Y., Zhang, L. and Fan, X. (2015). "Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design". Electronic Components & Technology Conference, pp. 1546-1552.
  10. Yoon, J. W., Kim, S. W. and Jung, S. B. (2006). "Effects of reflow and cooling conditions on interfacial reaction and IMC morphology of Sn-Cu/Ni solder joint". Journal of Alloys and Compounds, Vol. 415, pp. 56-61. https://doi.org/10.1016/j.jallcom.2005.03.124
  11. Syahirah, Z., Gopmath, R. and Tay, M. Y. (2012). "Advanced non-destructive fault isolation using computed tomography in flip-chip devices". Electronics Packaging Technology Conference(EPTC), IEEE 14th, pp. 537-541.
  12. Lai, P., Wang, Y., Liang, X., Kuang, X. and Zou, J. (2014). "Location techniques of failure analysis ESD damage in electronic component". Reliability, Maintainability and Safety (ICRMS), pp. 127-131.
  13. Mukai, K., Eastep, B., Kim, K., Gaherty L. and Kashyap, A. (2016). "A New Reliable Adhesion Enhancement Process for Directly Plating on Molding Compounds for Package Level EMI Shielding". IEEE 66th ECTC, pp. 1530-1537.